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arm64: dts: st: Add PCIe Root Complex mode on stm32mp251

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Add pcie_rc node to support STM32 MP25 PCIe driver based on the
DesignWare PCIe core configured as Root Complex mode

Supports Gen1/Gen2, single lane, MSI interrupts using the ARM GICv2m

Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://lore.kernel.org/r/20250820075411.1178729-10-christian.bruel@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Christian Bruel 2025-08-20 09:54:09 +02:00 committed by Alexandre Torgue
parent 7e4479c924
commit 0ecdf6d2f5
1 changed files with 44 additions and 0 deletions
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44
arch/arm64/boot/dts/st/stm32mp251.dtsi
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@ -122,6 +122,15 @@ intc: interrupt-controller@4ac00000 {
<0x0 0x4ac20000 0x0 0x20000>,
<0x0 0x4ac40000 0x0 0x20000>,
<0x0 0x4ac60000 0x0 0x20000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
v2m0: v2m@48090000 {
compatible = "arm,gic-v2m-frame";
reg = <0x0 0x48090000 0x0 0x1000>;
msi-controller;
};
};
psci {
@ -1654,6 +1663,41 @@ stmmac_axi_config_1: stmmac-axi-config {
snps,wr_osr_lmt = <0x7>;
};
};
pcie_rc: pcie@48400000 {
compatible = "st,stm32mp25-pcie-rc";
device_type = "pci";
reg = <0x48400000 0x400000>,
<0x10000000 0x10000>;
reg-names = "dbi", "config";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>,
<0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>,
<0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>;
dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>;
clocks = <&rcc CK_BUS_PCIE>;
resets = <&rcc PCIE_R>;
msi-parent = <&v2m0>;
access-controllers = <&rifsc 68>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
pcie@0,0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
phys = <&combophy PHY_TYPE_PCIE>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
};
bsec: efuse@44000000 {