ASoC: SOF: amd: add base platform support for ACP7.B/7.F

Add SOF support for ACP7.B and ACP7.F PCI revision based platforms.
This covers Kconfig/Makefile entries, register offset definitions,
DMA descriptor/channel/status paths, PGFSM power-on handling,
PCI device driver, I2S/DMIC DAI definitions, and IPC SW interrupt
trigger offset selection for ACP7.B/7.F.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://patch.msgid.link/20260701095759.1012929-3-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vijendar Mukunda 2026-07-01 15:25:03 +05:30 committed by Mark Brown
parent ec2332472f
commit 0ec5afad9d
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
8 changed files with 329 additions and 3 deletions

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@ -103,5 +103,15 @@ config SND_SOC_SOF_AMD_ACP70
Select this option for SOF support on
AMD ACP7.0/ACP7.1 version based platforms.
Say Y if you want to enable SOF on ACP7.0/ACP7.1 based platforms.
config SND_SOC_SOF_AMD_ACP7X
tristate "SOF support for ACP7.B/7.F platforms"
depends on SND_SOC_SOF_PCI
depends on AMD_NODE
select SND_SOC_SOF_AMD_COMMON
help
Select this option for SOF support on AMD ACP7.B and ACP7.F PCI
revision based platforms.
Say Y if you want to enable SOF on ACP7.B/7.F based platforms.
If unsure select "N".
endif

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@ -11,6 +11,7 @@ snd-sof-amd-rembrandt-y := pci-rmb.o rembrandt.o
snd-sof-amd-vangogh-y := pci-vangogh.o vangogh.o
snd-sof-amd-acp63-y := pci-acp63.o acp63.o
snd-sof-amd-acp70-y := pci-acp70.o acp70.o
snd-sof-amd-acp7x-y := pci-acp7x.o acp7x.o
obj-$(CONFIG_SND_SOC_SOF_AMD_COMMON) += snd-sof-amd-acp.o
obj-$(CONFIG_SND_SOC_SOF_AMD_RENOIR) += snd-sof-amd-renoir.o
@ -18,3 +19,4 @@ obj-$(CONFIG_SND_SOC_SOF_AMD_REMBRANDT) += snd-sof-amd-rembrandt.o
obj-$(CONFIG_SND_SOC_SOF_AMD_VANGOGH) += snd-sof-amd-vangogh.o
obj-$(CONFIG_SND_SOC_SOF_AMD_ACP63) += snd-sof-amd-acp63.o
obj-$(CONFIG_SND_SOC_SOF_AMD_ACP70) += snd-sof-amd-acp70.o
obj-$(CONFIG_SND_SOC_SOF_AMD_ACP7X) += snd-sof-amd-acp7x.o

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@ -68,12 +68,14 @@
#define ACP5X_PGFSM_BASE 0x1424
#define ACP6X_PGFSM_BASE 0x1024
#define ACP70_PGFSM_BASE ACP6X_PGFSM_BASE
#define ACP7X_PGFSM_BASE ACP6X_PGFSM_BASE
#define PGFSM_CONTROL_OFFSET 0x0
#define PGFSM_STATUS_OFFSET 0x4
#define ACP3X_CLKMUX_SEL 0x1424
#define ACP5X_CLKMUX_SEL 0x142C
#define ACP6X_CLKMUX_SEL 0x102C
#define ACP70_CLKMUX_SEL ACP6X_CLKMUX_SEL
#define ACP7X_CLKMUX_SEL ACP6X_CLKMUX_SEL
/* Registers from ACP_INTR block */
#define ACP3X_EXT_INTR_STAT 0x1808
@ -86,21 +88,31 @@
#define ACP70_EXTERNAL_INTR_CNTL ACP6X_EXTERNAL_INTR_CNTL
#define ACP70_EXT_INTR_STAT ACP6X_EXT_INTR_STAT
#define ACP70_EXT_INTR_STAT1 ACP6X_EXT_INTR_STAT1
#define ACP7X_EXTERNAL_INTR_ENB ACP6X_EXTERNAL_INTR_ENB
#define ACP7X_EXTERNAL_INTR_CNTL 0x1A04
#define ACP7X_EXT_INTR_STAT 0x1A1C
#define ACP7X_EXTERNAL_INTR_CNTL1 0x1A08
#define ACP7X_EXT_INTR_STAT1 0x1A20
#define ACP3X_DSP_SW_INTR_BASE 0x1814
#define ACP5X_DSP_SW_INTR_BASE 0x1814
#define ACP6X_DSP_SW_INTR_BASE 0x1808
#define ACP70_DSP_SW_INTR_BASE ACP6X_DSP_SW_INTR_BASE
#define ACP7X_DSP_SW_INTR_BASE 0x1860
#define DSP_SW_INTR_CNTL_OFFSET 0x0
#define DSP_SW_INTR_STAT_OFFSET 0x4
#define ACP7X_DSP_SW_INTR_STAT (ACP7X_DSP_SW_INTR_BASE + DSP_SW_INTR_STAT_OFFSET)
#define DSP_SW_INTR_TRIG_OFFSET 0x8
#define ACP7X_DSP_SW_INTR_TRIG_OFFSET 0x30
#define ACP3X_ERROR_STATUS 0x18C4
#define ACP6X_ERROR_STATUS 0x1A4C
#define ACP70_ERROR_STATUS ACP6X_ERROR_STATUS
#define ACP7X_ERROR_STATUS 0x1A88
#define ACP3X_AXI2DAGB_SEM_0 0x1880
#define ACP5X_AXI2DAGB_SEM_0 0x1884
#define ACP6X_AXI2DAGB_SEM_0 0x1874
#define ACP70_AXI2DAGB_SEM_0 ACP6X_AXI2DAGB_SEM_0
#define ACP7X_AXI2DAGB_SEM_0 0x18F4
/* ACP common registers to report errors related to I2S & SoundWire interfaces */
#define ACP3X_SW_I2S_ERROR_REASON 0x18C8
@ -123,6 +135,7 @@
#define ACP_SCRATCH_REG_0 0x10000
#define ACP6X_DSP_FUSION_RUNSTALL 0x0644
#define ACP70_DSP_FUSION_RUNSTALL ACP6X_DSP_FUSION_RUNSTALL
#define ACP7X_DSP_FUSION_RUNSTALL ACP6X_DSP_FUSION_RUNSTALL
/* Cache window registers */
#define ACP_DSP0_CACHE_OFFSET0 0x0420
@ -139,5 +152,9 @@
#define ACP70_SDW1_HOST_WAKE_STAT BIT(25)
#define ACP70_SDW0_PME_STAT BIT(26)
#define ACP70_SDW1_PME_STAT BIT(27)
#define ACP7X_DSP0_IDMA_ERROR_MASK 0x4B0
#define ACP7X_IDMA_ERROR_MASK 0x1FF9FF
#define ACP7X_ZSC_DSP_CTRL 0x001014
#define ACP7X_PME_EN ACP70_PME_EN
#endif

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@ -32,11 +32,20 @@ static void acpbus_trigger_host_to_dsp_swintr(struct acp_dev_data *adata)
struct snd_sof_dev *sdev = adata->dev;
const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
u32 swintr_trigger;
unsigned int swintr_trigger_reg_offset;
switch (adata->pci_rev) {
case ACP7B_PCI_ID:
case ACP7F_PCI_ID:
swintr_trigger_reg_offset = ACP7X_DSP_SW_INTR_TRIG_OFFSET;
break;
default:
swintr_trigger_reg_offset = DSP_SW_INTR_TRIG_OFFSET;
}
swintr_trigger = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->dsp_intr_base +
DSP_SW_INTR_TRIG_OFFSET);
swintr_trigger_reg_offset);
swintr_trigger |= 0x01;
snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_TRIG_OFFSET,
snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->dsp_intr_base + swintr_trigger_reg_offset,
swintr_trigger);
}

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@ -60,6 +60,8 @@ static void init_dma_descriptor(struct acp_dev_data *adata)
case ACP70_PCI_ID:
case ACP71_PCI_ID:
case ACP72_PCI_ID:
case ACP7B_PCI_ID:
case ACP7F_PCI_ID:
acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR;
acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR;
break;
@ -101,6 +103,8 @@ static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
case ACP70_PCI_ID:
case ACP71_PCI_ID:
case ACP72_PCI_ID:
case ACP7B_PCI_ID:
case ACP7F_PCI_ID:
acp_dma_cntl_0 = ACP70_DMA_CNTL_0;
acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS;
acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0;
@ -342,6 +346,8 @@ int acp_dma_status(struct acp_dev_data *adata, unsigned char ch)
case ACP70_PCI_ID:
case ACP71_PCI_ID:
case ACP72_PCI_ID:
case ACP7B_PCI_ID:
case ACP7F_PCI_ID:
acp_dma_ch_sts = ACP70_DMA_CH_STS;
break;
default:
@ -595,6 +601,11 @@ static int acp_power_on(struct snd_sof_dev *sdev)
acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK;
acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK;
break;
case ACP7B_PCI_ID:
case ACP7F_PCI_ID:
acp_pgfsm_status_mask = ACP7X_PGFSM_STATUS_MASK;
acp_pgfsm_cntl_mask = ACP7X_PGFSM_CNTL_POWER_ON_MASK;
break;
default:
return -EINVAL;
}
@ -604,7 +615,8 @@ static int acp_power_on(struct snd_sof_dev *sdev)
acp_pgfsm_cntl_mask);
ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,
!val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
!val, ACP_REG_POLL_INTERVAL,
ACP_REG_POLL_TIMEOUT_US);
if (ret < 0)
dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n");
@ -703,6 +715,13 @@ static int acp_init(struct snd_sof_dev *sdev)
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1);
break;
case ACP7B_PCI_ID:
case ACP7F_PCI_ID:
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_ZSC_DSP_CTRL, 0);
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_PME_EN, 1);
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_DSP0_IDMA_ERROR_MASK,
ACP7X_IDMA_ERROR_MASK);
break;
}
return 0;
}
@ -749,6 +768,8 @@ int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
case ACP72_PCI_ID:
enable = true;
break;
default:
break;
}
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable);

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@ -76,6 +76,12 @@
#define ACP70_PCI_ID 0x70
#define ACP71_PCI_ID 0x71
#define ACP72_PCI_ID 0x72
#define ACP7B_PCI_ID 0x7B
#define ACP7F_PCI_ID 0x7F
#define ACP7X_PGFSM_CNTL_POWER_ON_MASK 0x7F
#define ACP7X_PGFSM_STATUS_MASK 0xFFF
#define ACP7X_SRAM_PTE_OFFSET ACP6X_SRAM_PTE_OFFSET
#define HOST_BRIDGE_CZN 0x1630
#define HOST_BRIDGE_VGH 0x1645
@ -344,6 +350,9 @@ int sof_acp63_ops_init(struct snd_sof_dev *sdev);
extern struct snd_sof_dsp_ops sof_acp70_ops;
int sof_acp70_ops_init(struct snd_sof_dev *sdev);
extern struct snd_sof_dsp_ops sof_acp7x_ops;
int sof_acp7x_ops_init(struct snd_sof_dev *sdev);
struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);
/* Machine configuration */
int snd_amd_acp_find_config(struct pci_dev *pci);

142
sound/soc/sof/amd/acp7x.c Normal file
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@ -0,0 +1,142 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2025 Advanced Micro Devices, Inc.
//
// Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
/*
* Hardware interface for Audio DSP on ACP7.B/7.F platforms
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <sound/soc-acpi.h>
#include "../ops.h"
#include "../sof-audio.h"
#include "acp.h"
#include "acp-dsp-offset.h"
#define I2S_TDM0_INSTANCE 0
#define I2S_TDM1_INSTANCE 1
#define I2S_TDM2_INSTANCE 2
#define PDM0_DMIC_INSTANCE 3
#define PDM1_DMIC_INSTANCE 4
static struct snd_soc_dai_driver acp7x_sof_dai[] = {
[I2S_TDM0_INSTANCE] = {
.id = I2S_TDM0_INSTANCE,
.name = "acp-sof-i2s0",
.playback = {
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
},
.capture = {
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
/* Supporting only stereo for I2S HS controller capture */
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
},
[I2S_TDM1_INSTANCE] = {
.id = I2S_TDM1_INSTANCE,
.name = "acp-sof-i2s1",
.playback = {
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
},
.capture = {
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
/* Supporting only stereo for I2S BT controller capture */
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
},
[I2S_TDM2_INSTANCE] = {
.id = I2S_TDM2_INSTANCE,
.name = "acp-sof-i2s2",
.playback = {
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
},
.capture = {
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
/* Supporting only stereo for I2S SP controller capture */
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
},
[PDM0_DMIC_INSTANCE] = {
.id = PDM0_DMIC_INSTANCE,
.name = "acp-sof-dmic0",
.capture = {
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 4,
.rate_min = 8000,
.rate_max = 48000,
},
},
[PDM1_DMIC_INSTANCE] = {
.id = PDM1_DMIC_INSTANCE,
.name = "acp-sof-dmic1",
.capture = {
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 4,
.rate_min = 8000,
.rate_max = 96000,
},
},
};
struct snd_sof_dsp_ops sof_acp7x_ops;
EXPORT_SYMBOL_NS(sof_acp7x_ops, "SND_SOC_SOF_AMD_COMMON");
int sof_acp7x_ops_init(struct snd_sof_dev *sdev)
{
/* common defaults */
memcpy(&sof_acp7x_ops, &sof_acp_common_ops, sizeof(struct snd_sof_dsp_ops));
sof_acp7x_ops.drv = acp7x_sof_dai;
sof_acp7x_ops.num_drv = ARRAY_SIZE(acp7x_sof_dai);
return 0;
}

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@ -0,0 +1,116 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2025 Advanced Micro Devices, Inc. All rights reserved.
//
// Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
/*
* PCI interface for ACP7.B/7.F devices
*/
#include <linux/module.h>
#include <linux/pci.h>
#include <sound/sof.h>
#include <sound/soc-acpi.h>
#include "../ops.h"
#include "../sof-pci-dev.h"
#include "../../amd/mach-config.h"
#include "acp.h"
#include "acp-dsp-offset.h"
#define ACP7X_FUTURE_REG_ACLK_0 0x18e0
#define ACP7X_REG_START 0x1240000
#define ACP7X_REG_END 0x125C000
static const struct sof_amd_acp_desc acp7x_chip_info = {
.name = "acp7x",
.pgfsm_base = ACP7X_PGFSM_BASE,
.ext_intr_enb = ACP6X_EXTERNAL_INTR_ENB,
.ext_intr_cntl = ACP7X_EXTERNAL_INTR_CNTL,
.ext_intr_stat = ACP7X_EXT_INTR_STAT,
.ext_intr_stat1 = ACP7X_EXT_INTR_STAT1,
.dsp_intr_base = ACP7X_DSP_SW_INTR_BASE,
.acp_error_stat = ACP7X_ERROR_STATUS,
.sram_pte_offset = ACP7X_SRAM_PTE_OFFSET,
.hw_semaphore_offset = ACP7X_AXI2DAGB_SEM_0,
.fusion_dsp_offset = ACP7X_DSP_FUSION_RUNSTALL,
.probe_reg_offset = ACP7X_FUTURE_REG_ACLK_0,
.reg_start_addr = ACP7X_REG_START,
.reg_end_addr = ACP7X_REG_END,
};
static const struct sof_dev_desc acp7x_desc = {
.machines = snd_soc_acpi_amd_acp7x_sof_machines,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &acp7x_chip_info,
.ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
.ipc_default = SOF_IPC_TYPE_3,
.default_fw_path = {
[SOF_IPC_TYPE_3] = "amd/sof",
},
.default_tplg_path = {
[SOF_IPC_TYPE_3] = "amd/sof-tplg",
},
.default_fw_filename = {
[SOF_IPC_TYPE_3] = "sof-acp7x.ri",
},
.nocodec_tplg_filename = "sof-acp.tplg",
.ops = &sof_acp7x_ops,
.ops_init = sof_acp7x_ops_init,
};
static int acp7x_pci_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
{
unsigned int flag;
switch (pci->revision) {
case ACP7B_PCI_ID:
case ACP7F_PCI_ID:
break;
default:
return -ENODEV;
}
flag = snd_amd_acp_find_config(pci);
if (flag != FLAG_AMD_SOF && flag != FLAG_AMD_SOF_ONLY_DMIC)
return -ENODEV;
return sof_pci_probe(pci, pci_id);
}
static void acp7x_pci_remove(struct pci_dev *pci)
{
sof_pci_remove(pci);
}
/* PCI IDs */
static const struct pci_device_id acp7x_pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_PCI_DEV_ID),
.driver_data = (unsigned long)&acp7x_desc},
{ 0, }
};
MODULE_DEVICE_TABLE(pci, acp7x_pci_ids);
/* pci_driver definition */
static struct pci_driver snd_sof_pci_amd_acp7x_driver = {
.name = KBUILD_MODNAME,
.id_table = acp7x_pci_ids,
.probe = acp7x_pci_probe,
.remove = acp7x_pci_remove,
.driver = {
.pm = pm_ptr(&sof_pci_pm),
},
};
module_pci_driver(snd_sof_pci_amd_acp7x_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("ACP7X SOF Driver");
MODULE_IMPORT_NS("SND_SOC_SOF_AMD_COMMON");
MODULE_IMPORT_NS("SND_SOC_SOF_PCI_DEV");