From 0e78d93f714cc6724749d66dcbe9b3ebb44abf29 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Tue, 5 Dec 2017 20:43:50 +0800
Subject: [PATCH] arm: dts: rk3066a: Add operating-points-v2 property for cpu

This patch adds a new opp table for cpu.

Change-Id: I236fd158efc404c3d3611e3e7d1860cdf534aa57
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
---
 arch/arm/boot/dts/rk3066a.dtsi | 41 ++++++++++++++++++++++++++--------
 1 file changed, 32 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 54bc84611e14..3c06a25becfb 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -59,15 +59,7 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x0>;
-			operating-points = <
-				/* kHz    uV */
-				1008000 1075000
-				 816000 1025000
-				 600000 1025000
-				 504000 1000000
-				 312000  975000
-			>;
-			clock-latency = <40000>;
+			operating-points-v2 = <&cpu0_opp_table>;
 			clocks = <&cru ARMCLK>;
 		};
 		cpu@1 {
@@ -75,6 +67,37 @@ cpu@1 {
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x1>;
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+	};
+
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-312000000 {
+			opp-hz = /bits/ 64 <312000000>;
+			opp-microvolt = <1075000>;
+			clock-latency-ns = <40000>;
+			status = "disabled";
+		};
+		opp-504000000 {
+			opp-hz = /bits/ 64 <504000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <40000>;
+			status = "disabled";
+		};
+		opp-816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1125000>;
+			clock-latency-ns = <40000>;
+			status = "disabled";
+		};
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1125000>;
+			clock-latency-ns = <40000>;
+			status = "disabled";
 		};
 	};