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drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()

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Deduplicate the crtc_ timings comparisons.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2022-05-03 21:22:21 +03:00
parent 6cb07d2031
commit 0e5397d8c9
1 changed files with 18 additions and 27 deletions
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45
drivers/gpu/drm/i915/display/intel_display.c
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@ -6077,6 +6077,21 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
#define PIPE_CONF_CHECK_TIMINGS(name) do { \
PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
PIPE_CONF_CHECK_I(name.crtc_htotal); \
PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
PIPE_CONF_CHECK_I(name.crtc_vtotal); \
PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
} while (0)
/* This is required for BDW+ where there is only one set of registers for
* switching between high and low RR.
* This macro can be used whenever a comparison has to be made between one
@ -6194,33 +6209,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(framestart_delay);
PIPE_CONF_CHECK_I(msa_timing_delay);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
PIPE_CONF_CHECK_I(pixel_multiplier);
@ -6396,6 +6386,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
#undef PIPE_CONF_CHECK_FLAGS
#undef PIPE_CONF_CHECK_CLOCK_FUZZY
#undef PIPE_CONF_CHECK_COLOR_LUT
#undef PIPE_CONF_CHECK_TIMINGS
#undef PIPE_CONF_QUIRK
return ret;