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wifi: rtw89: wow: update WoWLAN reason register for different FW
Need to update WoWLAN wakeup reason register after firmware version 0.35.22.0 for RTL8922A, and 0.27.80.0 for RTL8852CE. Signed-off-by: Chih-Kang Chang <gary.chang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20240620055825.17592-3-pkshih@realtek.com
This commit is contained in:
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0065199f43
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0e52102177
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@ -4236,7 +4236,7 @@ struct rtw89_chip_info {
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const u32 *c2h_regs;
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const u32 *c2h_regs;
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struct rtw89_reg_def c2h_counter_reg;
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struct rtw89_reg_def c2h_counter_reg;
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const struct rtw89_page_regs *page_regs;
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const struct rtw89_page_regs *page_regs;
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u32 wow_reason_reg;
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const u32 *wow_reason_reg;
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bool cfo_src_fd;
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bool cfo_src_fd;
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bool cfo_hw_comp;
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bool cfo_hw_comp;
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const struct rtw89_reg_def *dcfo_comp;
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const struct rtw89_reg_def *dcfo_comp;
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@ -4346,6 +4346,7 @@ enum rtw89_fw_feature {
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RTW89_FW_FEATURE_NO_LPS_PG,
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RTW89_FW_FEATURE_NO_LPS_PG,
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RTW89_FW_FEATURE_BEACON_FILTER,
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RTW89_FW_FEATURE_BEACON_FILTER,
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RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
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RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
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RTW89_FW_FEATURE_WOW_REASON_V1,
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};
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};
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struct rtw89_fw_suit {
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struct rtw89_fw_suit {
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@ -675,10 +675,12 @@ static const struct __fw_feat_cfg fw_feat_tbl[] = {
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__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 36, 0, SCAN_OFFLOAD),
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__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 36, 0, SCAN_OFFLOAD),
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__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 40, 0, CRASH_TRIGGER),
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__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 40, 0, CRASH_TRIGGER),
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__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 56, 10, BEACON_FILTER),
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__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 56, 10, BEACON_FILTER),
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__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 80, 0, WOW_REASON_V1),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 30, 0, CRASH_TRIGGER),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 30, 0, CRASH_TRIGGER),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 11, 0, MACID_PAUSE_SLEEP),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 11, 0, MACID_PAUSE_SLEEP),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 35, 0, SCAN_OFFLOAD),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 35, 0, SCAN_OFFLOAD),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 12, 0, BEACON_FILTER),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 12, 0, BEACON_FILTER),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 22, 0, WOW_REASON_V1),
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};
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};
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static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,
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static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,
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@ -4659,4 +4659,10 @@ const struct rtw89_rfe_parms *
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rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
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rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
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const struct rtw89_rfe_parms *init);
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const struct rtw89_rfe_parms *init);
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enum rtw89_wow_wakeup_ver {
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RTW89_WOW_REASON_V0,
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RTW89_WOW_REASON_V1,
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RTW89_WOW_REASON_NUM,
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};
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#endif
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#endif
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@ -311,6 +311,8 @@
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#define B_AX_S1_LDO2PWRCUT_F BIT(23)
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#define B_AX_S1_LDO2PWRCUT_F BIT(23)
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#define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)
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#define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)
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#define R_AX_DBG_WOW 0x0504
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#define R_AX_SEC_CTRL 0x0C00
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#define R_AX_SEC_CTRL 0x0C00
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#define B_AX_SEC_IDMEM_SIZE_CONFIG_MASK GENMASK(17, 16)
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#define B_AX_SEC_IDMEM_SIZE_CONFIG_MASK GENMASK(17, 16)
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@ -4315,6 +4317,8 @@
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#define R_BE_WLCPU_PORT_PC 0x03FC
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#define R_BE_WLCPU_PORT_PC 0x03FC
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#define R_BE_DBG_WOW 0x0504
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#define R_BE_DCPU_PLATFORM_ENABLE 0x0888
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#define R_BE_DCPU_PLATFORM_ENABLE 0x0888
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#define B_BE_DCPU_SYM_DPLT_MEM_MUX_EN BIT(10)
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#define B_BE_DCPU_SYM_DPLT_MEM_MUX_EN BIT(10)
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#define B_BE_DCPU_WARM_EN BIT(9)
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#define B_BE_DCPU_WARM_EN BIT(9)
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@ -105,6 +105,10 @@ static const u32 rtw8851b_c2h_regs[RTW89_C2HREG_MAX] = {
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R_AX_C2HREG_DATA3
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R_AX_C2HREG_DATA3
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};
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};
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static const u32 rtw8851b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
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R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
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};
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static const struct rtw89_page_regs rtw8851b_page_regs = {
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static const struct rtw89_page_regs rtw8851b_page_regs = {
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.hci_fc_ctrl = R_AX_HCI_FC_CTRL,
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.hci_fc_ctrl = R_AX_HCI_FC_CTRL,
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.ch_page_ctrl = R_AX_CH_PAGE_CTRL,
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.ch_page_ctrl = R_AX_CH_PAGE_CTRL,
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@ -2509,7 +2513,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_regs = rtw8851b_c2h_regs,
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.c2h_regs = rtw8851b_c2h_regs,
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.page_regs = &rtw8851b_page_regs,
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.page_regs = &rtw8851b_page_regs,
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.wow_reason_reg = R_AX_C2HREG_DATA3 + 3,
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.wow_reason_reg = rtw8851b_wow_wakeup_regs,
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.cfo_src_fd = true,
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.cfo_src_fd = true,
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.cfo_hw_comp = true,
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.cfo_hw_comp = true,
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.dcfo_comp = &rtw8851b_dcfo_comp,
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.dcfo_comp = &rtw8851b_dcfo_comp,
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@ -398,6 +398,10 @@ static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = {
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R_AX_C2HREG_DATA3
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R_AX_C2HREG_DATA3
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};
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};
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static const u32 rtw8852a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
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R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
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};
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static const struct rtw89_page_regs rtw8852a_page_regs = {
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static const struct rtw89_page_regs rtw8852a_page_regs = {
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.hci_fc_ctrl = R_AX_HCI_FC_CTRL,
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.hci_fc_ctrl = R_AX_HCI_FC_CTRL,
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.ch_page_ctrl = R_AX_CH_PAGE_CTRL,
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.ch_page_ctrl = R_AX_CH_PAGE_CTRL,
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@ -2225,7 +2229,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
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.c2h_regs = rtw8852a_c2h_regs,
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.c2h_regs = rtw8852a_c2h_regs,
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.page_regs = &rtw8852a_page_regs,
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.page_regs = &rtw8852a_page_regs,
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.wow_reason_reg = R_AX_C2HREG_DATA3 + 3,
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.wow_reason_reg = rtw8852a_wow_wakeup_regs,
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.cfo_src_fd = false,
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.cfo_src_fd = false,
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.cfo_hw_comp = false,
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.cfo_hw_comp = false,
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.dcfo_comp = &rtw8852a_dcfo_comp,
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.dcfo_comp = &rtw8852a_dcfo_comp,
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@ -76,6 +76,10 @@ static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = {
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R_AX_C2HREG_DATA3
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R_AX_C2HREG_DATA3
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};
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};
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static const u32 rtw8852b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
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R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
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};
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static const struct rtw89_page_regs rtw8852b_page_regs = {
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static const struct rtw89_page_regs rtw8852b_page_regs = {
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.hci_fc_ctrl = R_AX_HCI_FC_CTRL,
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.hci_fc_ctrl = R_AX_HCI_FC_CTRL,
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.ch_page_ctrl = R_AX_CH_PAGE_CTRL,
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.ch_page_ctrl = R_AX_CH_PAGE_CTRL,
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@ -1026,7 +1030,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_regs = rtw8852b_c2h_regs,
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.c2h_regs = rtw8852b_c2h_regs,
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.page_regs = &rtw8852b_page_regs,
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.page_regs = &rtw8852b_page_regs,
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.wow_reason_reg = R_AX_C2HREG_DATA3 + 3,
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.wow_reason_reg = rtw8852b_wow_wakeup_regs,
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.cfo_src_fd = true,
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.cfo_src_fd = true,
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.cfo_hw_comp = true,
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.cfo_hw_comp = true,
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.dcfo_comp = &rtw8852b_dcfo_comp,
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.dcfo_comp = &rtw8852b_dcfo_comp,
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@ -73,6 +73,10 @@ static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = {
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R_AX_C2HREG_DATA3_V1
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R_AX_C2HREG_DATA3_V1
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};
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};
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static const u32 rtw8852c_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
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R_AX_C2HREG_DATA3_V1 + 3, R_AX_DBG_WOW,
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};
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static const struct rtw89_page_regs rtw8852c_page_regs = {
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static const struct rtw89_page_regs rtw8852c_page_regs = {
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.hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1,
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.hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1,
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.ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1,
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.ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1,
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@ -3007,7 +3011,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_regs = rtw8852c_c2h_regs,
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.c2h_regs = rtw8852c_c2h_regs,
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.page_regs = &rtw8852c_page_regs,
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.page_regs = &rtw8852c_page_regs,
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.wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3,
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.wow_reason_reg = rtw8852c_wow_wakeup_regs,
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.cfo_src_fd = false,
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.cfo_src_fd = false,
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.cfo_hw_comp = false,
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.cfo_hw_comp = false,
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.dcfo_comp = &rtw8852c_dcfo_comp,
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.dcfo_comp = &rtw8852c_dcfo_comp,
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@ -85,6 +85,10 @@ static const u32 rtw8922a_c2h_regs[RTW89_H2CREG_MAX] = {
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R_BE_C2HREG_DATA3
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R_BE_C2HREG_DATA3
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};
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};
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static const u32 rtw8922a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
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R_AX_C2HREG_DATA3_V1 + 3, R_BE_DBG_WOW,
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};
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static const struct rtw89_page_regs rtw8922a_page_regs = {
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static const struct rtw89_page_regs rtw8922a_page_regs = {
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.hci_fc_ctrl = R_BE_HCI_FC_CTRL,
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.hci_fc_ctrl = R_BE_HCI_FC_CTRL,
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.ch_page_ctrl = R_BE_CH_PAGE_CTRL,
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.ch_page_ctrl = R_BE_CH_PAGE_CTRL,
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@ -2609,7 +2613,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
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.c2h_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_regs = rtw8922a_c2h_regs,
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.c2h_regs = rtw8922a_c2h_regs,
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.page_regs = &rtw8922a_page_regs,
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.page_regs = &rtw8922a_page_regs,
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.wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3,
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.wow_reason_reg = rtw8922a_wow_wakeup_regs,
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.cfo_src_fd = true,
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.cfo_src_fd = true,
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.cfo_hw_comp = true,
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.cfo_hw_comp = true,
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.dcfo_comp = NULL,
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.dcfo_comp = NULL,
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@ -723,13 +723,18 @@ static void rtw89_wow_show_wakeup_reason(struct rtw89_dev *rtwdev)
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{
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{
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struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
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struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
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struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt;
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struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt;
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u32 wow_reason_reg = rtwdev->chip->wow_reason_reg;
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struct cfg80211_wowlan_nd_info nd_info;
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struct cfg80211_wowlan_nd_info nd_info;
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struct cfg80211_wowlan_wakeup wakeup = {
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struct cfg80211_wowlan_wakeup wakeup = {
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.pattern_idx = -1,
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.pattern_idx = -1,
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};
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};
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u32 wow_reason_reg;
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u8 reason;
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u8 reason;
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if (RTW89_CHK_FW_FEATURE(WOW_REASON_V1, &rtwdev->fw))
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wow_reason_reg = rtwdev->chip->wow_reason_reg[RTW89_WOW_REASON_V1];
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else
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wow_reason_reg = rtwdev->chip->wow_reason_reg[RTW89_WOW_REASON_V0];
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reason = rtw89_read8(rtwdev, wow_reason_reg);
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reason = rtw89_read8(rtwdev, wow_reason_reg);
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switch (reason) {
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switch (reason) {
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case RTW89_WOW_RSN_RX_DEAUTH:
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case RTW89_WOW_RSN_RX_DEAUTH:
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