From 0de9b836a3bc1cd30578ae2c4463d09afd85ed3d Mon Sep 17 00:00:00 2001 From: Keguang Zhang Date: Wed, 15 Jul 2026 19:05:24 +0800 Subject: [PATCH] pwm: loongson: Reload PWM configuration through counter reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Loongson PWM controller latches the LOW and PERIOD registers only at the start of each PWM period. After disabling and re-enabling the PWM, the controller resumes from the previous counter value and completes the current period before re-latching the updated LOW and PERIOD values. Reset the PWM counter when disabling the PWM and release it when enabling the PWM so that the updated LOW and PERIOD values are latched before the PWM starts running again. Fixes: 2b62c89448dd ("pwm: Add Loongson PWM controller support") Signed-off-by: Keguang Zhang Link: https://patch.msgid.link/20260715-pwm-loongson-fix-v3-2-0aab2847eaa7@gmail.com [ukleinek: Note LOW refers to the register currently named LOONGSON_PWM_REG_DUTY. That name is wrong, the fix is still under discussion.] Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-loongson.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pwm/pwm-loongson.c b/drivers/pwm/pwm-loongson.c index f2fb35b7af2b..98c809bde2b3 100644 --- a/drivers/pwm/pwm-loongson.c +++ b/drivers/pwm/pwm-loongson.c @@ -99,6 +99,7 @@ static void pwm_loongson_disable(struct pwm_chip *chip, struct pwm_device *pwm) struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); val = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); + val |= LOONGSON_PWM_CTRL_REG_RST; val &= ~LOONGSON_PWM_CTRL_REG_EN; pwm_loongson_writel(ddata, val, LOONGSON_PWM_REG_CTRL); } @@ -109,6 +110,7 @@ static int pwm_loongson_enable(struct pwm_chip *chip, struct pwm_device *pwm) struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); val = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); + val &= ~LOONGSON_PWM_CTRL_REG_RST; val |= LOONGSON_PWM_CTRL_REG_EN; pwm_loongson_writel(ddata, val, LOONGSON_PWM_REG_CTRL);