mirror of
https://github.com/torvalds/linux.git
synced 2026-06-05 04:56:13 +02:00
Renesas DTS updates for v6.17
- Add SPI FLASH, camera, and Ethernet support on the RZ/G3E SoC and/or
the RZ/G3E SoM and SMARC Carrier-II EVK development board,
- Add Ethernet, USB2, and PMIC support on the RZ/V2H and RZ/V2N SoCs
and EVK boards,
- Add timer, I2C, watchdog, and GPU support on the RZ/V2N SoC and the
RZ/V2N EVK board,
- Add debug LED support for the RZN1D-DB development board,
- Improve PCIe clock description on the Retronix Sparrow Hawk board,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.17
- Add SPI FLASH, camera, and Ethernet support on the RZ/G3E SoC and/or
the RZ/G3E SoM and SMARC Carrier-II EVK development board,
- Add Ethernet, USB2, and PMIC support on the RZ/V2H and RZ/V2N SoCs
and EVK boards,
- Add timer, I2C, watchdog, and GPU support on the RZ/V2N SoC and the
RZ/V2N EVK board,
- Add debug LED support for the RZN1D-DB development board,
- Improve PCIe clock description on the Retronix Sparrow Hawk board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
arm64: dts: renesas: r9a09g047: Add GBETH nodes
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Rename fixed regulator node names
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add RAA215300 PMIC
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add RAA215300 PMIC
arm64: dts: renesas: rcar-gen3: Add bootph-all to sysinfo EEPROMs
arm64: dts: renesas: sparrow-hawk: Describe split PCIe clock
arm64: dts: renesas: r8a779g0: Describe PCIe root ports
arm64: dts: renesas: ebisu: Add CAN0 support
ARM: dts: renesas: r9a06g032: Add second clock input to RTC
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2.0 support
arm64: dts: renesas: r9a09g056: Add USB2.0 support
arm64: dts: renesas: r8a779g3-sparrow-hawk: Sort DTS
ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe debug LEDs
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 support
PCI/pwrctrl: Add optional slot clock for PCI slots
arm64: dts: renesas: r9a09g057: Add USB2.0 support
arm64: dts: renesas: r9a09g047e57-smarc: Enable CRU, CSI support
arm64: dts: renesas: renesas-smarc2: Enable I2C0 node
arm64: dts: renesas: r9a09g047e57-smarc: Add I2C0 pincontrol
arm64: dts: renesas: r9a09g047: Add CRU, CSI2 nodes
...
Link: https://lore.kernel.org/r/cover.1751026664.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
0dc89a2546
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@ -10,6 +10,7 @@
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|||
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/net/pcs-rzn1-miic.h>
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#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
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@ -86,7 +87,66 @@ switch-8 {
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debounce-interval = <20>;
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gpios = <&pca9698 15 GPIO_ACTIVE_LOW>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led-dbg0 {
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gpios = <&pca9698 0 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DEBUG;
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function-enumerator = <0>;
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};
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led-dbg1 {
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gpios = <&pca9698 1 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DEBUG;
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function-enumerator = <1>;
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};
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led-dbg2 {
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gpios = <&pca9698 2 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DEBUG;
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function-enumerator = <2>;
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};
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led-dbg3 {
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gpios = <&pca9698 3 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DEBUG;
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function-enumerator = <3>;
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};
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led-dbg4 {
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gpios = <&pca9698 4 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DEBUG;
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function-enumerator = <4>;
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};
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led-dbg5 {
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gpios = <&pca9698 5 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DEBUG;
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function-enumerator = <5>;
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};
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led-dbg6 {
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gpios = <&pca9698 6 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DEBUG;
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function-enumerator = <6>;
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};
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led-dbg7 {
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gpios = <&pca9698 7 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DEBUG;
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function-enumerator = <7>;
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};
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};
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};
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@ -111,6 +171,10 @@ ð_miic {
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renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
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};
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&ext_rtc_clk {
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clock-frequency = <32768>;
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};
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&gmac2 {
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status = "okay";
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phy-mode = "gmii";
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@ -73,8 +73,8 @@ rtc0: rtc@40006000 {
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<GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "alarm", "timer", "pps";
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clocks = <&sysctrl R9A06G032_HCLK_RTC>;
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clock-names = "hclk";
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clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>;
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clock-names = "hclk", "xtal";
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power-domains = <&sysctrl>;
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status = "disabled";
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};
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@ -156,6 +156,9 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb
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dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
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dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
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dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtbo
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r9a09g047e57-smarc-cru-csi-ov5645-dtbs := r9a09g047e57-smarc.dtb r9a09g047e57-smarc-cru-csi-ov5645.dtbo
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dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtb
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dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk.dtb
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@ -174,6 +174,7 @@ phy0: ethernet-phy@0 {
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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bootph-all;
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status = "okay";
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clock-frequency = <400000>;
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@ -230,6 +231,7 @@ eeprom@50 {
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compatible = "rohm,br24t01", "atmel,24c01";
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reg = <0x50>;
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pagesize = <8>;
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bootph-all;
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};
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};
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@ -308,6 +308,7 @@ &hsusb {
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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bootph-all;
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status = "okay";
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ak4613: codec@10 {
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@ -449,6 +450,7 @@ eeprom@50 {
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compatible = "rohm,br24t01", "atmel,24c01";
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reg = <0x50>;
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pagesize = <8>;
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bootph-all;
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};
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};
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@ -327,9 +327,18 @@ phy0: ethernet-phy@0 {
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};
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};
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&can0 {
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pinctrl-0 = <&can0_pins>;
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pinctrl-names = "default";
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/* Please only enable canfd or can0 */
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/* status = "okay"; */
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};
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&canfd {
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pinctrl-0 = <&canfd0_pins>;
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pinctrl-names = "default";
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/* Please only enable canfd or can0 */
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status = "okay";
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channel0 {
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@ -503,6 +512,7 @@ cs2000: clk-multiplier@4f {
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};
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&i2c_dvfs {
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bootph-all;
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status = "okay";
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clock-frequency = <400000>;
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@ -526,6 +536,7 @@ eeprom@50 {
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compatible = "rohm,br24t01", "atmel,24c01";
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reg = <0x50>;
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pagesize = <8>;
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bootph-all;
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};
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};
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@ -579,6 +590,11 @@ avb_pins: avb {
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function = "avb";
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};
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can0_pins: can0 {
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groups = "can0_data";
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function = "can0";
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};
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canfd0_pins: canfd0 {
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groups = "canfd0_data";
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function = "canfd0";
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@ -798,6 +798,16 @@ pciec0: pcie@e65d0000 {
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<0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
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snps,enable-cdm-check;
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status = "disabled";
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/* PCIe bridge, Root Port */
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pciec0_rp: pci@0,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x0 0x0 0x0 0x0 0x0>;
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compatible = "pciclass,0604";
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device_type = "pci";
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ranges;
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};
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};
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pciec1: pcie@e65d8000 {
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@ -835,6 +845,16 @@ pciec1: pcie@e65d8000 {
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<0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
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snps,enable-cdm-check;
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status = "disabled";
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/* PCIe bridge, Root Port */
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pciec1_rp: pci@0,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x0 0x0 0x0 0x0 0x0>;
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compatible = "pciclass,0604";
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device_type = "pci";
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ranges;
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};
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};
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pciec0_ep: pcie-ep@e65d0000 {
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|
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@ -130,6 +130,13 @@ mini_dp_con_in: endpoint {
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};
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};
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/* Page 26 / PCIe.0/1 CLK */
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pcie_refclk: clk-x8 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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reg_1p2v: regulator-1p2v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.2V";
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@ -404,6 +411,14 @@ i2c0_mux2: i2c@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Page 26 / PCIe.0/1 CLK */
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pcie_clk: clk@68 {
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compatible = "renesas,9fgv0441";
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reg = <0x68>;
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clocks = <&pcie_refclk>;
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#clock-cells = <1>;
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};
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};
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i2c0_mux3: i2c@3 {
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|
|
@ -487,26 +502,38 @@ msiof1_snd_endpoint: endpoint {
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/* Page 26 / 2230 Key M M.2 */
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&pcie0_clkref {
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clock-frequency = <100000000>;
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status = "disabled";
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};
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&pciec0 {
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clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>;
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reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pciec0_rp {
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clocks = <&pcie_clk 1>;
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vpcie3v3-supply = <®_3p3v>;
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};
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/* Page 25 / PCIe to USB */
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&pcie1_clkref {
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clock-frequency = <100000000>;
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status = "disabled";
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};
|
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|
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&pciec1 {
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clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>;
|
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/* uPD720201 is PCIe Gen2 x1 device */
|
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num-lanes = <1>;
|
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reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
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status = "okay";
|
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};
|
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|
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&pciec1_rp {
|
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clocks = <&pcie_clk 3>;
|
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vpcie3v3-supply = <®_3p3v>;
|
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};
|
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|
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&pfc {
|
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pinctrl-0 = <&scif_clk_pins>;
|
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pinctrl-names = "default";
|
||||
|
|
@ -679,19 +706,6 @@ sound_clk_pins: sound-clk {
|
|||
};
|
||||
};
|
||||
|
||||
/* Page 30 / Audio_Codec */
|
||||
&rcar_sound {
|
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pinctrl-0 = <&sound_clk_pins>;
|
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pinctrl-names = "default";
|
||||
|
||||
/* It is used for ADG output as DA7212_MCLK */
|
||||
|
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/* audio_clkout */
|
||||
clock-frequency = <12288000>; /* 48 kHz groups */
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
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/* Page 31 / FAN */
|
||||
&pwm0 {
|
||||
pinctrl-0 = <&pwm0_pins>;
|
||||
|
|
@ -720,6 +734,19 @@ &pwm7 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
/* Page 30 / Audio_Codec */
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* It is used for ADG output as DA7212_MCLK */
|
||||
|
||||
/* audio_clkout */
|
||||
clock-frequency = <12288000>; /* 48 kHz groups */
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Page 16 / QSPI_FLASH */
|
||||
&rpc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
|
|
|
|||
|
|
@ -280,6 +280,27 @@ sys: system-controller@10430000 {
|
|||
resets = <&cpg 0x30>;
|
||||
};
|
||||
|
||||
xspi: spi@11030000 {
|
||||
compatible = "renesas,r9a09g047-xspi";
|
||||
reg = <0 0x11030000 0 0x10000>,
|
||||
<0 0x20000000 0 0x10000000>;
|
||||
reg-names = "regs", "dirmap";
|
||||
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "pulse", "err_pulse";
|
||||
clocks = <&cpg CPG_MOD 0x9f>,
|
||||
<&cpg CPG_MOD 0xa0>,
|
||||
<&cpg CPG_CORE R9A09G047_SPI_CLK_SPI>,
|
||||
<&cpg CPG_MOD 0xa1>;
|
||||
clock-names = "ahb", "axi", "spi", "spix2";
|
||||
resets = <&cpg 0xa3>, <&cpg 0xa4>;
|
||||
reset-names = "hresetn", "aresetn";
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif0: serial@11c01400 {
|
||||
compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";
|
||||
reg = <0 0x11c01400 0 0x400>;
|
||||
|
|
@ -669,6 +690,284 @@ sdhi2_vqmmc: vqmmc-regulator {
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@15c30000 {
|
||||
compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth",
|
||||
"snps,dwmac-5.20";
|
||||
reg = <0 0x15c30000 0 0x10000>;
|
||||
clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
|
||||
<&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>,
|
||||
<&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
|
||||
<&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref",
|
||||
"tx", "rx", "tx-180", "rx-180";
|
||||
interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "tx-queue-0", "tx-queue-1",
|
||||
"tx-queue-2", "tx-queue-3";
|
||||
resets = <&cpg 0xb0>;
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup0>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup0>;
|
||||
snps,txpbl = <32>;
|
||||
snps,rxpbl = <32>;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup0: rx-queues-config {
|
||||
snps,rx-queues-to-use = <4>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup0: tx-queues-config {
|
||||
snps,tx-queues-to-use = <4>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eth1: ethernet@15c40000 {
|
||||
compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth",
|
||||
"snps,dwmac-5.20";
|
||||
reg = <0 0x15c40000 0 0x10000>;
|
||||
clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
|
||||
<&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>,
|
||||
<&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
|
||||
<&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref",
|
||||
"tx", "rx", "tx-180", "rx-180";
|
||||
interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "tx-queue-0", "tx-queue-1",
|
||||
"tx-queue-2", "tx-queue-3";
|
||||
resets = <&cpg 0xb1>;
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup1>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup1>;
|
||||
snps,txpbl = <32>;
|
||||
snps,rxpbl = <32>;
|
||||
status = "disabled";
|
||||
|
||||
mdio1: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup1: rx-queues-config {
|
||||
snps,rx-queues-to-use = <4>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup1: tx-queues-config {
|
||||
snps,tx-queues-to-use = <4>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cru: video@16000000 {
|
||||
compatible = "renesas,r9a09g047-cru";
|
||||
reg = <0 0x16000000 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD 0xd3>,
|
||||
<&cpg CPG_MOD 0xd4>,
|
||||
<&cpg CPG_MOD 0xd2>;
|
||||
clock-names = "video", "apb", "axi";
|
||||
interrupts = <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 840 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 841 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "image_conv", "axi_mst_err",
|
||||
"vd_addr_wend", "sd_addr_wend",
|
||||
"vsd_addr_wend";
|
||||
resets = <&cpg 0xc5>, <&cpg 0xc6>;
|
||||
reset-names = "presetn", "aresetn";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
crucsi2: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csi2cru>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
csi2: csi2@16000400 {
|
||||
compatible = "renesas,r9a09g047-csi2", "renesas,r9a09g057-csi2";
|
||||
reg = <0 0x16000400 0 0xc00>;
|
||||
interrupts = <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xd3>, <&cpg CPG_MOD 0xd4>;
|
||||
clock-names = "video", "apb";
|
||||
resets = <&cpg 0xc5>, <&cpg 0xc7>;
|
||||
reset-names = "presetn", "cmn-rstb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
csi2cru: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&crucsi2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,lpi_en;
|
||||
snps,wr_osr_lmt = <0xf>;
|
||||
snps,rd_osr_lmt = <0xf>;
|
||||
snps,blen = <16 8 4 0 0 0 0>;
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree overlay for the RZ/G3E SMARC EVK with OV5645 camera
|
||||
* connected to CSI and CRU enabled.
|
||||
*
|
||||
* Copyright (C) 2025 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
|
||||
|
||||
#define OV5645_PARENT_I2C i2c0
|
||||
#include "rz-smarc-cru-csi-ov5645.dtsi"
|
||||
|
||||
&ov5645 {
|
||||
enable-gpios = <&pinctrl RZG3E_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&pinctrl RZG3E_GPIO(D, 7) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
|
@ -74,6 +74,11 @@ &can_transceiver1 {
|
|||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
canfd_pins: canfd {
|
||||
can1_pins: can1 {
|
||||
|
|
@ -87,6 +92,11 @@ can4_pins: can4 {
|
|||
};
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
pinmux = <RZG3E_PORT_PINMUX(D, 4, 4)>, /* SCL0 */
|
||||
<RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */
|
||||
};
|
||||
|
||||
scif_pins: scif {
|
||||
pins = "SCIF_TXD", "SCIF_RXD";
|
||||
renesas,output-impedance = <1>;
|
||||
|
|
|
|||
|
|
@ -123,6 +123,35 @@ L3_CA55: cache-controller-0 {
|
|||
};
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-630000000 {
|
||||
opp-hz = /bits/ 64 <630000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
|
||||
opp-315000000 {
|
||||
opp-hz = /bits/ 64 <315000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
|
||||
opp-157500000 {
|
||||
opp-hz = /bits/ 64 <157500000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
|
||||
opp-78750000 {
|
||||
opp-hz = /bits/ 64 <78750000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
|
||||
opp-19687500 {
|
||||
opp-hz = /bits/ 64 <19687500>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
|
|
@ -177,6 +206,126 @@ sys: system-controller@10430000 {
|
|||
resets = <&cpg 0x30>;
|
||||
};
|
||||
|
||||
ostm0: timer@11800000 {
|
||||
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x11800000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x43>;
|
||||
resets = <&cpg 0x6d>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm1: timer@11801000 {
|
||||
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x11801000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x44>;
|
||||
resets = <&cpg 0x6e>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm2: timer@14000000 {
|
||||
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x14000000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x45>;
|
||||
resets = <&cpg 0x6f>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm3: timer@14001000 {
|
||||
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x14001000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x46>;
|
||||
resets = <&cpg 0x70>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm4: timer@12c00000 {
|
||||
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x12c00000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x47>;
|
||||
resets = <&cpg 0x71>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm5: timer@12c01000 {
|
||||
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x12c01000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x48>;
|
||||
resets = <&cpg 0x72>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm6: timer@12c02000 {
|
||||
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x12c02000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x49>;
|
||||
resets = <&cpg 0x73>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm7: timer@12c03000 {
|
||||
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x12c03000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x4a>;
|
||||
resets = <&cpg 0x74>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt0: watchdog@11c00400 {
|
||||
compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
|
||||
reg = <0 0x11c00400 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
resets = <&cpg 0x75>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt1: watchdog@14400000 {
|
||||
compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
|
||||
reg = <0 0x14400000 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
resets = <&cpg 0x76>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt2: watchdog@13000000 {
|
||||
compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
|
||||
reg = <0 0x13000000 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
resets = <&cpg 0x77>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt3: watchdog@13000400 {
|
||||
compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
|
||||
reg = <0 0x13000400 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
resets = <&cpg 0x78>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif: serial@11c01400 {
|
||||
compatible = "renesas,scif-r9a09g056",
|
||||
"renesas,scif-r9a09g057";
|
||||
|
|
@ -199,6 +348,217 @@ scif: serial@11c01400 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@14400400 {
|
||||
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14400400 0 0x400>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 507 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 506 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x94>;
|
||||
resets = <&cpg 0x98>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@14400800 {
|
||||
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14400800 0 0x400>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 509 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 508 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x95>;
|
||||
resets = <&cpg 0x99>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@14400c00 {
|
||||
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14400c00 0 0x400>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 511 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 510 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x96>;
|
||||
resets = <&cpg 0x9a>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@14401000 {
|
||||
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14401000 0 0x400>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 513 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 512 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x97>;
|
||||
resets = <&cpg 0x9b>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@14401400 {
|
||||
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14401400 0 0x400>;
|
||||
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 515 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 514 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x98>;
|
||||
resets = <&cpg 0x9c>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@14401800 {
|
||||
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14401800 0 0x400>;
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 517 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 516 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x99>;
|
||||
resets = <&cpg 0x9d>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@14401c00 {
|
||||
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14401c00 0 0x400>;
|
||||
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 519 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x9a>;
|
||||
resets = <&cpg 0x9e>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@14402000 {
|
||||
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14402000 0 0x400>;
|
||||
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 521 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 520 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x9b>;
|
||||
resets = <&cpg 0x9f>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c8: i2c@11c01000 {
|
||||
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x11c01000 0 0x400>;
|
||||
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 523 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 522 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x93>;
|
||||
resets = <&cpg 0xa0>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu: gpu@14850000 {
|
||||
compatible = "renesas,r9a09g056-mali",
|
||||
"arm,mali-bifrost";
|
||||
reg = <0x0 0x14850000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "job", "mmu", "gpu", "event";
|
||||
clocks = <&cpg CPG_MOD 0xf0>,
|
||||
<&cpg CPG_MOD 0xf1>,
|
||||
<&cpg CPG_MOD 0xf2>;
|
||||
clock-names = "gpu", "bus", "bus_ace";
|
||||
resets = <&cpg 0xdd>,
|
||||
<&cpg 0xde>,
|
||||
<&cpg 0xdf>;
|
||||
reset-names = "rst", "axi_rst", "ace_rst";
|
||||
power-domains = <&cpg>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@14900000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0x14900000 0 0x20000>,
|
||||
|
|
@ -209,6 +569,72 @@ gic: interrupt-controller@14900000 {
|
|||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
ohci0: usb@15800000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0x15800000 0 0x100>;
|
||||
interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
|
||||
resets = <&usb20phyrst>, <&cpg 0xac>;
|
||||
phys = <&usb2_phy0 1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@15800100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0x15800100 0 0x100>;
|
||||
interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
|
||||
resets = <&usb20phyrst>, <&cpg 0xac>;
|
||||
phys = <&usb2_phy0 2>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci0>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy0: usb-phy@15800200 {
|
||||
compatible = "renesas,usb2-phy-r9a09g056", "renesas,usb2-phy-r9a09g057";
|
||||
reg = <0 0x15800200 0 0x700>;
|
||||
interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>,
|
||||
<&cpg CPG_CORE R9A09G056_USB2_0_CLK_CORE0>;
|
||||
clock-names = "fck", "usb_x1";
|
||||
resets = <&usb20phyrst>;
|
||||
#phy-cells = <1>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb: usb@15820000 {
|
||||
compatible = "renesas,usbhs-r9a09g056",
|
||||
"renesas,rzg2l-usbhs";
|
||||
reg = <0 0x15820000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>;
|
||||
resets = <&usb20phyrst>,
|
||||
<&cpg 0xae>;
|
||||
phys = <&usb2_phy0 3>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb20phyrst: usb20phy-reset@15830000 {
|
||||
compatible = "renesas,r9a09g056-usb2phy-reset",
|
||||
"renesas,r9a09g057-usb2phy-reset";
|
||||
reg = <0 0x15830000 0 0x10000>;
|
||||
clocks = <&cpg CPG_MOD 0xb6>;
|
||||
resets = <&cpg 0xaf>;
|
||||
power-domains = <&cpg>;
|
||||
#reset-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: mmc@15c00000 {
|
||||
compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
|
||||
reg = <0x0 0x15c00000 0 0x10000>;
|
||||
|
|
@ -268,6 +694,215 @@ sdhi2_vqmmc: vqmmc-regulator {
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@15c30000 {
|
||||
compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth",
|
||||
"snps,dwmac-5.20";
|
||||
reg = <0 0x15c30000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "tx-queue-0", "tx-queue-1",
|
||||
"tx-queue-2", "tx-queue-3";
|
||||
clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
|
||||
<&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>,
|
||||
<&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
|
||||
<&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref",
|
||||
"tx", "rx", "tx-180", "rx-180";
|
||||
resets = <&cpg 0xb0>;
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup0>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup0>;
|
||||
snps,txpbl = <32>;
|
||||
snps,rxpbl = <32>;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup0: rx-queues-config {
|
||||
snps,rx-queues-to-use = <4>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup0: tx-queues-config {
|
||||
snps,tx-queues-to-use = <4>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eth1: ethernet@15c40000 {
|
||||
compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth",
|
||||
"snps,dwmac-5.20";
|
||||
reg = <0 0x15c40000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "tx-queue-0", "tx-queue-1",
|
||||
"tx-queue-2", "tx-queue-3";
|
||||
clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
|
||||
<&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>,
|
||||
<&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
|
||||
<&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref",
|
||||
"tx", "rx", "tx-180", "rx-180";
|
||||
resets = <&cpg 0xb1>;
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup1>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup1>;
|
||||
snps,txpbl = <32>;
|
||||
snps,rxpbl = <32>;
|
||||
status = "disabled";
|
||||
|
||||
mdio1: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup1: rx-queues-config {
|
||||
snps,rx-queues-to-use = <4>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup1: tx-queues-config {
|
||||
snps,tx-queues-to-use = <4>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,lpi_en;
|
||||
snps,wr_osr_lmt = <0xf>;
|
||||
snps,rd_osr_lmt = <0xf>;
|
||||
snps,blen = <16 8 4 0 0 0 0>;
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
|
|
@ -15,6 +15,15 @@ / {
|
|||
compatible = "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a09g056";
|
||||
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c7;
|
||||
i2c8 = &i2c8;
|
||||
mmc1 = &sdhi1;
|
||||
serial0 = &scif;
|
||||
};
|
||||
|
|
@ -30,6 +39,15 @@ memory@48000000 {
|
|||
reg = <0x0 0x48000000 0x1 0xf8000000>;
|
||||
};
|
||||
|
||||
reg_0p8v: regulator-0p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-0.8V";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
|
|
@ -48,13 +66,232 @@ vqmmc_sdhi1: regulator-vqmmc-sdhi1 {
|
|||
gpios-states = <0>;
|
||||
states = <3300000 0>, <1800000 1>;
|
||||
};
|
||||
|
||||
/* 32.768kHz crystal */
|
||||
x6: x6-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&audio_extal_clk {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-0 = <ð0_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð1 {
|
||||
pinctrl-0 = <ð1_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
mali-supply = <®_0p8v>;
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
pinctrl-0 = <&i2c6_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
pinctrl-0 = <&i2c7_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
pinctrl-0 = <&i2c8_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
raa215300: pmic@12 {
|
||||
compatible = "renesas,raa215300";
|
||||
reg = <0x12>, <0x6f>;
|
||||
reg-names = "main", "rtc";
|
||||
clocks = <&x6>;
|
||||
clock-names = "xin";
|
||||
};
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
rxc-skew-psec = <0>;
|
||||
txc-skew-psec = <0>;
|
||||
rxdv-skew-psec = <0>;
|
||||
txdv-skew-psec = <0>;
|
||||
rxd0-skew-psec = <0>;
|
||||
rxd1-skew-psec = <0>;
|
||||
rxd2-skew-psec = <0>;
|
||||
rxd3-skew-psec = <0>;
|
||||
txd0-skew-psec = <0>;
|
||||
txd1-skew-psec = <0>;
|
||||
txd2-skew-psec = <0>;
|
||||
txd3-skew-psec = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
rxc-skew-psec = <0>;
|
||||
txc-skew-psec = <0>;
|
||||
rxdv-skew-psec = <0>;
|
||||
txdv-skew-psec = <0>;
|
||||
rxd0-skew-psec = <0>;
|
||||
rxd1-skew-psec = <0>;
|
||||
rxd2-skew-psec = <0>;
|
||||
rxd3-skew-psec = <0>;
|
||||
txd0-skew-psec = <0>;
|
||||
txd1-skew-psec = <0>;
|
||||
txd2-skew-psec = <0>;
|
||||
txd3-skew-psec = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
eth0_pins: eth0 {
|
||||
pins = "ET0_TXC_TXCLK";
|
||||
output-enable;
|
||||
};
|
||||
|
||||
eth1_pins: eth0 {
|
||||
pins = "ET1_TXC_TXCLK";
|
||||
output-enable;
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
pinmux = <RZV2N_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
|
||||
<RZV2N_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
pinmux = <RZV2N_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
|
||||
<RZV2N_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
pinmux = <RZV2N_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
|
||||
<RZV2N_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
|
||||
};
|
||||
|
||||
i2c3_pins: i2c3 {
|
||||
pinmux = <RZV2N_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
|
||||
<RZV2N_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
|
||||
};
|
||||
|
||||
i2c6_pins: i2c6 {
|
||||
pinmux = <RZV2N_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
|
||||
<RZV2N_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
|
||||
/* There are no pull-up resistors on the EVK, so enable the internal pull-up */
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
i2c7_pins: i2c7 {
|
||||
pinmux = <RZV2N_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
|
||||
<RZV2N_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
|
||||
/* There are no pull-up resistors on the EVK, so enable the internal pull-up */
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
i2c8_pins: i2c8 {
|
||||
pinmux = <RZV2N_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
|
||||
<RZV2N_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
|
||||
};
|
||||
|
||||
scif_pins: scif {
|
||||
pins = "SCIF_TXD", "SCIF_RXD";
|
||||
renesas,output-impedance = <1>;
|
||||
|
|
@ -85,6 +322,16 @@ sd1-dat-cmd {
|
|||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb20_pins: usb20 {
|
||||
ovc {
|
||||
pinmux = <RZV2N_PORT_PINMUX(9, 6, 14)>; /* OVC */
|
||||
};
|
||||
|
||||
vbus {
|
||||
pinmux = <RZV2N_PORT_PINMUX(9, 5, 14)>; /* VBUS */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qextal_clk {
|
||||
|
|
@ -112,3 +359,18 @@ &sdhi1 {
|
|||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb20phyrst {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb20_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -807,6 +807,119 @@ gic: interrupt-controller@14900000 {
|
|||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
ohci0: usb@15800000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0x15800000 0 0x100>;
|
||||
interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
|
||||
resets = <&usb20phyrst>, <&cpg 0xac>;
|
||||
phys = <&usb2_phy0 1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@15810000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0x15810000 0 0x100>;
|
||||
interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
|
||||
resets = <&usb21phyrst>, <&cpg 0xad>;
|
||||
phys = <&usb2_phy1 1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@15800100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0x15800100 0 0x100>;
|
||||
interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
|
||||
resets = <&usb20phyrst>, <&cpg 0xac>;
|
||||
phys = <&usb2_phy0 2>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci0>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@15810100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0x15810100 0 0x100>;
|
||||
interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
|
||||
resets = <&usb21phyrst>, <&cpg 0xad>;
|
||||
phys = <&usb2_phy1 2>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci1>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy0: usb-phy@15800200 {
|
||||
compatible = "renesas,usb2-phy-r9a09g057";
|
||||
reg = <0 0x15800200 0 0x700>;
|
||||
interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>,
|
||||
<&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>;
|
||||
clock-names = "fck", "usb_x1";
|
||||
resets = <&usb20phyrst>;
|
||||
#phy-cells = <1>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy1: usb-phy@15810200 {
|
||||
compatible = "renesas,usb2-phy-r9a09g057";
|
||||
reg = <0 0x15810200 0 0x700>;
|
||||
interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb4>,
|
||||
<&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>;
|
||||
clock-names = "fck", "usb_x1";
|
||||
resets = <&usb21phyrst>;
|
||||
#phy-cells = <1>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb: usb@15820000 {
|
||||
compatible = "renesas,usbhs-r9a09g057",
|
||||
"renesas,rzg2l-usbhs";
|
||||
reg = <0 0x15820000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>;
|
||||
resets = <&usb20phyrst>,
|
||||
<&cpg 0xae>;
|
||||
phys = <&usb2_phy0 3>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb20phyrst: usb20phy-reset@15830000 {
|
||||
compatible = "renesas,r9a09g057-usb2phy-reset";
|
||||
reg = <0 0x15830000 0 0x10000>;
|
||||
clocks = <&cpg CPG_MOD 0xb6>;
|
||||
resets = <&cpg 0xaf>;
|
||||
power-domains = <&cpg>;
|
||||
#reset-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb21phyrst: usb21phy-reset@15840000 {
|
||||
compatible = "renesas,r9a09g057-usb2phy-reset";
|
||||
reg = <0 0x15840000 0 0x10000>;
|
||||
clocks = <&cpg CPG_MOD 0xb7>;
|
||||
resets = <&cpg 0xaf>;
|
||||
power-domains = <&cpg>;
|
||||
#reset-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: mmc@15c00000 {
|
||||
compatible = "renesas,sdhi-r9a09g057";
|
||||
reg = <0x0 0x15c00000 0 0x10000>;
|
||||
|
|
@ -866,6 +979,215 @@ sdhi2_vqmmc: vqmmc-regulator {
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@15c30000 {
|
||||
compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth",
|
||||
"snps,dwmac-5.20";
|
||||
reg = <0 0x15c30000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "tx-queue-0", "tx-queue-1",
|
||||
"tx-queue-2", "tx-queue-3";
|
||||
clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
|
||||
<&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>,
|
||||
<&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
|
||||
<&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref",
|
||||
"tx", "rx", "tx-180", "rx-180";
|
||||
resets = <&cpg 0xb0>;
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup0>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup0>;
|
||||
snps,txpbl = <32>;
|
||||
snps,rxpbl = <32>;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup0: rx-queues-config {
|
||||
snps,rx-queues-to-use = <4>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup0: tx-queues-config {
|
||||
snps,tx-queues-to-use = <4>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eth1: ethernet@15c40000 {
|
||||
compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth",
|
||||
"snps,dwmac-5.20";
|
||||
reg = <0 0x15c40000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
|
||||
"rx-queue-0", "rx-queue-1", "rx-queue-2",
|
||||
"rx-queue-3", "tx-queue-0", "tx-queue-1",
|
||||
"tx-queue-2", "tx-queue-3";
|
||||
clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
|
||||
<&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>,
|
||||
<&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
|
||||
<&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref",
|
||||
"tx", "rx", "tx-180", "rx-180";
|
||||
resets = <&cpg 0xb1>;
|
||||
power-domains = <&cpg>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
rx-fifo-depth = <8192>;
|
||||
tx-fifo-depth = <8192>;
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8;
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup1>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup1>;
|
||||
snps,txpbl = <32>;
|
||||
snps,rxpbl = <32>;
|
||||
status = "disabled";
|
||||
|
||||
mdio1: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup1: rx-queues-config {
|
||||
snps,rx-queues-to-use = <4>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
snps,map-to-dma-channel = <0>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
snps,map-to-dma-channel = <1>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
snps,map-to-dma-channel = <2>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
snps,map-to-dma-channel = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup1: tx-queues-config {
|
||||
snps,tx-queues-to-use = <4>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x2>;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x4>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,lpi_en;
|
||||
snps,wr_osr_lmt = <0xf>;
|
||||
snps,rd_osr_lmt = <0xf>;
|
||||
snps,blen = <16 8 4 0 0 0 0>;
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@ / {
|
|||
compatible = "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a09g057";
|
||||
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
|
|
@ -43,7 +45,7 @@ memory@240000000 {
|
|||
reg = <0x2 0x40000000 0x2 0x00000000>;
|
||||
};
|
||||
|
||||
reg_0p8v: regulator0 {
|
||||
reg_0p8v: regulator-0p8v {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "fixed-0.8V";
|
||||
|
|
@ -53,7 +55,7 @@ reg_0p8v: regulator0 {
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator1 {
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "fixed-3.3V";
|
||||
|
|
@ -72,17 +74,54 @@ vqmmc_sdhi1: regulator-vccq-sdhi1 {
|
|||
gpios-states = <0>;
|
||||
states = <3300000 0>, <1800000 1>;
|
||||
};
|
||||
|
||||
/* 32.768kHz crystal */
|
||||
x6: x6-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&audio_extal_clk {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-0 = <ð0_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð1 {
|
||||
pinctrl-0 = <ð1_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
mali-supply = <®_0p8v>;
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -137,6 +176,61 @@ &i2c8 {
|
|||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
raa215300: pmic@12 {
|
||||
compatible = "renesas,raa215300";
|
||||
reg = <0x12>, <0x6f>;
|
||||
reg-names = "main", "rtc";
|
||||
clocks = <&x6>;
|
||||
clock-names = "xin";
|
||||
};
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
rxc-skew-psec = <0>;
|
||||
txc-skew-psec = <0>;
|
||||
rxdv-skew-psec = <0>;
|
||||
txdv-skew-psec = <0>;
|
||||
rxd0-skew-psec = <0>;
|
||||
rxd1-skew-psec = <0>;
|
||||
rxd2-skew-psec = <0>;
|
||||
rxd3-skew-psec = <0>;
|
||||
txd0-skew-psec = <0>;
|
||||
txd1-skew-psec = <0>;
|
||||
txd2-skew-psec = <0>;
|
||||
txd3-skew-psec = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
rxc-skew-psec = <0>;
|
||||
txc-skew-psec = <0>;
|
||||
rxdv-skew-psec = <0>;
|
||||
txdv-skew-psec = <0>;
|
||||
rxd0-skew-psec = <0>;
|
||||
rxd1-skew-psec = <0>;
|
||||
rxd2-skew-psec = <0>;
|
||||
rxd3-skew-psec = <0>;
|
||||
txd0-skew-psec = <0>;
|
||||
txd1-skew-psec = <0>;
|
||||
txd2-skew-psec = <0>;
|
||||
txd3-skew-psec = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm0 {
|
||||
|
|
@ -172,6 +266,16 @@ &ostm7 {
|
|||
};
|
||||
|
||||
&pinctrl {
|
||||
eth0_pins: eth0 {
|
||||
pins = "ET0_TXC_TXCLK";
|
||||
output-enable;
|
||||
};
|
||||
|
||||
eth1_pins: eth0 {
|
||||
pins = "ET1_TXC_TXCLK";
|
||||
output-enable;
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
pinmux = <RZV2H_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
|
||||
<RZV2H_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
|
||||
|
|
@ -237,6 +341,26 @@ sd1_cd {
|
|||
pinmux = <RZV2H_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
|
||||
};
|
||||
};
|
||||
|
||||
usb20_pins: usb20 {
|
||||
ovc {
|
||||
pinmux = <RZV2H_PORT_PINMUX(9, 6, 14)>; /* OVC */
|
||||
};
|
||||
|
||||
vbus {
|
||||
pinmux = <RZV2H_PORT_PINMUX(9, 5, 14)>; /* VBUS */
|
||||
};
|
||||
};
|
||||
|
||||
usb21_pins: usb21 {
|
||||
ovc {
|
||||
pinmux = <RZV2H_PORT_PINMUX(6, 7, 14)>; /* OVC */
|
||||
};
|
||||
|
||||
vbus {
|
||||
pinmux = <RZV2H_PORT_PINMUX(6, 6, 14)>; /* VBUS */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qextal_clk {
|
||||
|
|
@ -266,6 +390,28 @@ &sdhi1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb20phyrst {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb21phyrst {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb20_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
pinctrl-0 = <&usb21_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ chosen {
|
|||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
serial3 = &scif0;
|
||||
mmc1 = &sdhi1;
|
||||
};
|
||||
|
|
@ -58,6 +59,11 @@ &canfd {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -182,6 +182,15 @@ sd2-pwen {
|
|||
pinmux = <RZG3E_PORT_PINMUX(K, 2, 1)>; /* SD2PWEN */
|
||||
};
|
||||
};
|
||||
|
||||
xspi_pins: xspi0 {
|
||||
pinmux = <RZG3E_PORT_PINMUX(M, 0, 0)>, /* XSPI0_IO0 */
|
||||
<RZG3E_PORT_PINMUX(M, 1, 0)>, /* XSPI0_IO1 */
|
||||
<RZG3E_PORT_PINMUX(M, 2, 0)>, /* XSPI0_IO2 */
|
||||
<RZG3E_PORT_PINMUX(M, 3, 0)>, /* XSPI0_IO3 */
|
||||
<RZG3E_PORT_PINMUX(L, 0, 0)>, /* XSPI0_CKP */
|
||||
<RZG3E_PORT_PINMUX(L, 1, 0)>; /* XSPI0_CS0 */
|
||||
};
|
||||
};
|
||||
|
||||
&qextal_clk {
|
||||
|
|
@ -245,3 +254,40 @@ &sdhi2_vqmmc {
|
|||
&wdt1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xspi {
|
||||
pinctrl-0 = <&xspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
vcc-supply = <®_1p8v>;
|
||||
m25p,fast-read;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "bl2";
|
||||
reg = <0x00000000 0x00060000>;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "fip";
|
||||
reg = <0x00060000 0x007a0000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "user";
|
||||
reg = <0x800000 0x800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -592,6 +592,7 @@ csa_dvfs: adc@7f {
|
|||
};
|
||||
|
||||
&i2c_dvfs {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -625,6 +626,7 @@ eeprom@50 {
|
|||
compatible = "rohm,br24t01", "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -244,6 +244,7 @@ versaclock5: clock-generator@6a {
|
|||
};
|
||||
|
||||
&i2c_dvfs {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -277,6 +278,7 @@ eeprom@50 {
|
|||
compatible = "rohm,br24t01", "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
|
|
@ -30,6 +31,7 @@ static int pci_pwrctrl_slot_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct pci_pwrctrl_slot_data *slot;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
slot = devm_kzalloc(dev, sizeof(*slot), GFP_KERNEL);
|
||||
|
|
@ -55,6 +57,12 @@ static int pci_pwrctrl_slot_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
goto err_regulator_disable;
|
||||
|
||||
clk = devm_clk_get_optional_enabled(dev, NULL);
|
||||
if (IS_ERR(clk)) {
|
||||
return dev_err_probe(dev, PTR_ERR(clk),
|
||||
"Failed to enable slot clock\n");
|
||||
}
|
||||
|
||||
pci_pwrctrl_init(&slot->ctx, dev);
|
||||
|
||||
ret = devm_pci_pwrctrl_device_set_ready(dev, &slot->ctx);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user