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clk: zte: Introduce a driver for zx297520v3 matrix clocks
This clock controller controls high speed devices: CPU, DMA, RAM, SDIO, Ethernet. The only non-clock, non-reset registers I have spotted here are hardware spinlocks. Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Stefan Dösinger
Brian Masney
parent
913e9c3b02
commit
0d852cd2ae
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@ -812,6 +812,528 @@ static const struct zx_clk_data zx297520v3_topclk_data = {
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.num_exports = ARRAY_SIZE(zx297520v3_top_exports),
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};
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enum matrix_clock_ids {
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ZX_CLK_MATRIX_OSC26M_D4,
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ZX_CLK_MATRIX_MPLL_D2_PREGATE,
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ZX_CLK_MATRIX_MPLL_D4_PREGATE,
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ZX_CLK_MATRIX_MPLL_D6_PREGATE,
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ZX_CLK_MATRIX_MPLL_D8_PREGATE,
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ZX_CLK_MATRIX_MPLL_D12_PREGATE,
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ZX_CLK_MATRIX_MPLL_D16_PREGATE,
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ZX_CLK_MATRIX_GPLL_D2_D2_PREGATE,
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ZX_CLK_MATRIX_GPLL_D2_D4_PREGATE,
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ZX_CLK_MATRIX_DPLL_D2_PREGATE,
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ZX_CLK_MATRIX_DPLL_D4_PREGATE,
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ZX_CLK_MATRIX_MPLL_D16,
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ZX_CLK_MATRIX_MPLL_D12,
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ZX_CLK_MATRIX_MPLL_D8,
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ZX_CLK_MATRIX_MPLL_D6,
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ZX_CLK_MATRIX_MPLL_D4,
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ZX_CLK_MATRIX_MPLL_D2,
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ZX_CLK_MATRIX_DPLL_D4,
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ZX_CLK_MATRIX_DPLL_D2,
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ZX_CLK_MATRIX_GPLL_D2_D4,
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ZX_CLK_MATRIX_GPLL_D2_D2,
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ZX_CLK_CPU_MUX,
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ZX_CLK_ZSP_MUX,
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ZX_CLK_DDR_CTRL_MUX,
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ZX_CLK_SD0_MUX,
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ZX_CLK_SD1_MUX,
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ZX_CLK_NAND_MUX,
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ZX_CLK_EDCP_MUX,
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ZX_CLK_TDM_MUX,
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ZX_CLK_AXI_MUX,
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ZX_CLK_SYS_TIMER_WCLK,
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ZX_CLK_CPU_WCLK,
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ZX_CLK_CPU_PCLK,
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ZX_CLK_ZSP_WCLK,
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ZX_CLK_ZSP_PCLK,
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ZX_CLK_DDR_CTRL_PCLK,
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ZX_CLK_DDR_CTRL_WCLK,
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ZX_CLK_SD0_PCLK,
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ZX_CLK_SD0_WCLK,
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ZX_CLK_SD0_CDET,
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ZX_CLK_SD1_PCLK,
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ZX_CLK_SD1_WCLK,
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ZX_CLK_SD1_CDET,
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ZX_CLK_NAND_WCLK,
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ZX_CLK_NAND_PCLK,
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ZX_CLK_LTE_MODEM_WCLK,
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ZX_CLK_LTE_MODEM_PCLK,
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ZX_CLK_EDCP_PCLK,
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ZX_CLK_EDCP_WCLK,
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ZX_CLK_RFFE_WCLK,
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ZX_CLK_SSC_WCLK,
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ZX_CLK_SSC_PCLK,
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ZX_CLK_PDCFG_WCLK,
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ZX_CLK_PDCFG_PCLK,
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ZX_CLK_MBOX_PCLK,
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ZX_CLK_SRAM0_PCLK,
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ZX_CLK_GSM_CFG_PCLK,
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ZX_CLK_GMAC_WCLK,
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ZX_CLK_GMAC_PCLK,
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ZX_CLK_GMAC_AHB,
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ZX_CLK_AXI_WCLK,
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ZX_CLK_DMA_PCLK,
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ZX_CLK_VOU_WCLK,
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ZX_CLK_VOU_PCLK,
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ZX_CLK_TOLSP_MPLL_D5_WCLK,
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ZX_CLK_TOLSP_MPLL_D4_WCLK,
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ZX_CLK_TOLSP_MPLL_D6_WCLK,
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ZX_CLK_TOLSP_MPLL_D8_WCLK,
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ZX_CLK_TOLSP_MPLL_D12_WCLK,
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ZX_CLK_TOLSP_OSC26M_WCLK,
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ZX_CLK_TOLSP_OSC32K_WCLK,
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ZX_CLK_TOLSP_PCLK,
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ZX_CLK_TOLSP_TDM_WCLK,
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ZX_CLK_TOLSP_DPLL_D4_WCLK,
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};
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/*
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* For devices which have a working driver the work clock can be figured out by gating off registers
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* in topcrm+0x140. This is used for devices where I can't interpret the register contents yet.
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*/
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static const struct zx_parent_desc matrix_unk = PARENT_FW("wclk-osc26m");
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static const struct zx_parent_desc cpu_sel[] = {
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PARENT_FW("wclk-osc26m"),
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PARENT_FW("mpll"), /* 624 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D2), /* 312 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */
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};
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/*
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* Figuring these values out is a bit tricky. The best liveness check of the ZSP is reading its TCM
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* at 0x81000000. If it is clocked up and out of reset reading it will succeed. Otherwise, reading
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* will stall. Value 1 depends on topcrm+0x140, bit 13, but not any matrixcrm+0x118 gate, so it is
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* likely dpll without a div. Mux value 2 depends on 0x118 bit 5, so mpll-d2. Mux value 3 depends on
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* 0x118 bit 4, so mpll-d4. Mux value 0 in turn depends on topcrm+0x140, bit 24 (osc26m), so it
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* follows the usual pattern that mux 0 is osc26m.
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*
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* If the firmware is running and fed with initialization data it will start writing status messages
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* on UART1. An interruption of these messages or a failure to respond to rpmsg is not proof that
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* the ZSP's clock has been disabled. The firmware's workings depend on regular timer and LTE device
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* IRQs, so one of these devices might have been stopped instead.
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*/
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static const struct zx_parent_desc zsp_sel[] = {
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PARENT_FW("wclk-osc26m"),
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PARENT_FW("dpll"), /* 491.52 MHz, boot default */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D2), /* 312 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */
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};
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/*
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* We can't realistically change DDR speed while running an OS out of DDR (it reads garbage for a
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* short while on transition), but we need to know if we have to keep gpll alive. 32 MB devices use
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* 200 MHz, while 64/128 MB ones use 156 MHz.
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*/
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static const struct zx_parent_desc ddr_ctrl_sel[] = {
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */
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PARENT_FW("gpll"), /* 200 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D6), /* 104 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D8), /* 78 MHz */
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};
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static const struct zx_parent_desc sd0_sel[] = {
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PARENT_FW("wclk-osc26m"),
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */
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PARENT_FW("gpll-d2"), /* 100 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D8), /* 78 MHz */
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PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D2), /* 50 MHz */
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PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D4), /* 25 MHz */
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};
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static const struct zx_parent_desc sd1_sel[] = {
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PARENT_FW("wclk-osc26m"),
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PARENT_FW("gpll-d2"), /* 100 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D8), /* 78 MHz */
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PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D2), /* 50 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D16), /* 39 MHz */
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PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D4), /* 25 MHz */
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};
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/*
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* ZTE's kernel puts the high frequency first, but this is against the usual convention on this SoC.
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* I don't have any device that has a raw NAND controller though.
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*/
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static const struct zx_parent_desc nand_sel[] = {
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PARENT_FW("wclk-osc26m"),
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */
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};
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static const struct zx_parent_desc edcp_sel[] = {
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PARENT_FW("wclk-osc26m"),
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */
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PARENT_FW("mpll-d5"), /* 124.8 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D6), /* 104 MHz */
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};
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/*
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* The 122.88 MHz selection of value 1 is given in ZTE's kernel and matches up to observation: Print
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* the TDM counter at regular intervals and look at its increase at values 0/1/2. It increases by
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* about 310*26 for value 0, 310*122.88 for value 1 and 310*104 for value 2.
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*
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* Mux value 1 is gated off by matrix+0x118 bit 8. Values 2 and 3 are both gated off by 0x118 bit 3,
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* suggesting that they select the same parent.
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*/
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static const struct zx_parent_desc tdm_sel[] = {
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PARENT_FW("wclk-osc26m"),
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PARENT_ID(ZX_CLK_MATRIX_DPLL_D4), /* 122.88 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D6), /* 104 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D6),
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};
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/*
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* ZTE's firmware uses 0x128 as the PHY's vote and names 0x120 as "PS" and 0x124 as "AP" vote.
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* However, their cpufreq driver ultimately uses the "PS" define and thus writes to 0x120, which can
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* be observed in the running system.
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*/
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#define ZX297520V3_AXI_AP_VOTE 0x120
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static const struct zx_parent_desc axi_sel[] = {
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PARENT_FW("wclk-osc26m"),
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */
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PARENT_FW("mpll-d5"), /* 124.8 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D6), /* 104 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D8), /* 78 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D12), /* 52 MHz */
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D16), /* 39 MHz */
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PARENT_ID(ZX_CLK_MATRIX_OSC26M_D4), /* 6.5 MHz */
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};
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static const struct zx_clock zx297520v3_matrix_clocks[] = {
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[ZX_CLK_MATRIX_OSC26M_D4] = FIXED_DIV("matrix-osc26m-d4", PARENT_FW("wclk-osc26m"), 4),
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[ZX_CLK_MATRIX_MPLL_D2_PREGATE] = FIXED_DIV("matrix-mpll-d2-pregate", PARENT_FW("mpll"), 2),
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[ZX_CLK_MATRIX_MPLL_D4_PREGATE] = FIXED_DIV("matrix-mpll-d4-pregate", PARENT_FW("mpll"), 4),
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/* div 5: provided as a separate line from topcrm */
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[ZX_CLK_MATRIX_MPLL_D6_PREGATE] = FIXED_DIV("matrix-mpll-d6-pregate", PARENT_FW("mpll"), 6),
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[ZX_CLK_MATRIX_MPLL_D8_PREGATE] = FIXED_DIV("matrix-mpll-d8-pregate", PARENT_FW("mpll"), 8),
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[ZX_CLK_MATRIX_MPLL_D12_PREGATE] = FIXED_DIV("matrix-mpll-d12-pregate", PARENT_FW("mpll"),
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12),
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[ZX_CLK_MATRIX_MPLL_D16_PREGATE] = FIXED_DIV("matrix-mpll-d16-pregate", PARENT_FW("mpll"),
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16),
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[ZX_CLK_MATRIX_GPLL_D2_D2_PREGATE] = FIXED_DIV("matrix-gpll-d2-d2-pregate",
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PARENT_FW("gpll-d2"), 2),
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[ZX_CLK_MATRIX_GPLL_D2_D4_PREGATE] = FIXED_DIV("matrix-gpll-d2-d4-pregate",
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PARENT_FW("gpll-d2"), 4),
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[ZX_CLK_MATRIX_DPLL_D2_PREGATE] = FIXED_DIV("matrix-dpll-d2-pregate", PARENT_FW("dpll"), 2),
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[ZX_CLK_MATRIX_DPLL_D4_PREGATE] = FIXED_DIV("matrix-dpll-d4-pregate", PARENT_FW("dpll"), 4),
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/*
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* Matrix distribution gates: Every matrix-generated subdivision of the input PLLs
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* has a gate in 0x118. The original inputs from topcrm (mpll 624, mpll 124.8, gpll 200,
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* gpll 100, dpll 491.52) do not.
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*
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* Bit 8 is consumed by TDM and the frequency dpll/4 holds up to observation. Bit 9 is
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* consumed by an unknown device and the frequency is guessed from the pattern that lower
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* bits gate lower frequencies.
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*/
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[ZX_CLK_MATRIX_MPLL_D16] = GATE("matrix-mpll-d16",
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D16_PREGATE), 0x118, 0,
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ZX297520V3_AXI_CANDIDATE),
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[ZX_CLK_MATRIX_MPLL_D12] = GATE("matrix-mpll-d12",
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D12_PREGATE), 0x118, 1,
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ZX297520V3_AXI_CANDIDATE),
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[ZX_CLK_MATRIX_MPLL_D8] = GATE("matrix-mpll-d8",
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D8_PREGATE), 0x118, 2,
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ZX297520V3_AXI_CANDIDATE),
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[ZX_CLK_MATRIX_MPLL_D6] = GATE("matrix-mpll-d6",
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D6_PREGATE), 0x118, 3,
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ZX297520V3_AXI_CANDIDATE),
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[ZX_CLK_MATRIX_MPLL_D4] = GATE("matrix-mpll-d4",
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D4_PREGATE), 0x118, 4,
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ZX297520V3_AXI_CANDIDATE),
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[ZX_CLK_MATRIX_MPLL_D2] = GATE("matrix-mpll-d2",
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PARENT_ID(ZX_CLK_MATRIX_MPLL_D2_PREGATE), 0x118, 5, 0),
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[ZX_CLK_MATRIX_DPLL_D4] = GATE("matrix-dpll-d4",
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PARENT_ID(ZX_CLK_MATRIX_DPLL_D4_PREGATE), 0x118, 8, 0),
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[ZX_CLK_MATRIX_DPLL_D2] = GATE("matrix-dpll-d2",
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PARENT_ID(ZX_CLK_MATRIX_DPLL_D2_PREGATE), 0x118, 9, 0),
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[ZX_CLK_MATRIX_GPLL_D2_D4] = GATE("matrix-gpll-d2-d4",
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PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D4_PREGATE),
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0x118, 12, 0),
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[ZX_CLK_MATRIX_GPLL_D2_D2] = GATE("matrix-gpll-d2-d2",
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PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D2_PREGATE),
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0x118, 13, 0),
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[ZX_CLK_CPU_MUX] = MUX("cpu-mux", cpu_sel, 0x20, 0, 2),
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[ZX_CLK_ZSP_MUX] = MUX("zsp-mux", zsp_sel, 0x30, 0, 2),
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[ZX_CLK_DDR_CTRL_MUX] = MUX("ddr-ctrl-mux", ddr_ctrl_sel, 0x50, 0, 2),
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[ZX_CLK_SD0_MUX] = MUX("sd0-mux", sd0_sel, 0x50, 4, 3),
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[ZX_CLK_SD1_MUX] = MUX("sd1-mux", sd1_sel, 0x50, 8, 3),
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[ZX_CLK_NAND_MUX] = MUX("nand-mux", nand_sel, 0x50, 12, 2),
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[ZX_CLK_EDCP_MUX] = MUX("edcp-mux", edcp_sel, 0x50, 16, 2),
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[ZX_CLK_TDM_MUX] = MUX("tdm-mux", tdm_sel, 0x50, 24, 2),
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[ZX_CLK_AXI_MUX] = MUX("axi-mux", axi_sel, ZX297520V3_AXI_AP_VOTE, 0, 3),
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/*
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* This bit cuts off the clock signal to the ARM architected timer, which the kernel uses
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* as its main timer. It isn't critical per se - there are plenty of proprietary timers
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* available that could be used - but the arm arch timer binding does not accept a clock, so
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* this CCF driver won't know if the timer is in use.
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*
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* This clock is fed by the osc26m gate in topcrm+0x140 - this critical clock here protects
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* its parent.
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*
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* Registers 0x148, 0x14c, 0x150, 0x154 allow setting and clearing the timer counter. To
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* set the timer, load a value into 0x148 (high 32 bits) and 0x14c (low 32 bits), then
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* toggle 0x150 to 1. 0x150 will automatically reset to 0. 0x154 sets the timer to some
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* "clear" value, but this value isn't 0.
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*/
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[ZX_CLK_SYS_TIMER_WCLK] = GATE("sys-timer-wclk", PARENT_FW("wclk-osc26m"), 0x144, 1,
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CLK_IS_CRITICAL),
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/*
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* Both 0x24 and 0x28 bits 1 and 2 stop the CPU. There is also a bit in topcrm+0x138, which
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* ZTE's uboot calls "A53 reset", which also stops the CPU. I can't really tell the
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* difference between matrix+0x28 and top+0x138. The clock (matrix+0x24) can be disabled
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* and enabled from the Cortex M0 and it will nicely stop and restart the A53, retaining
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* all state.
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*/
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[ZX_CLK_CPU_WCLK] = GATE("cpu-wclk", PARENT_ID(ZX_CLK_CPU_MUX), 0x24, 1,
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CLK_IS_CRITICAL),
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[ZX_CLK_CPU_PCLK] = GATE("cpu-pclk", clk_main[0], 0x24, 2, CLK_IS_CRITICAL),
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/*
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* There are a lot more controls in matrix+0x100. 13-16 appear to be 4 different AXI
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* channels for different priorities. Bit 19 appears to be the DDR PHY wclk.
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*
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* The important task is to keep gpll enabled if the bootloader selected a gpll-based rate
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* for RAM.
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*/
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[ZX_CLK_DDR_CTRL_PCLK] = GATE("ddr-ctrl-pclk", clk_main[0], 0x100, 17, CLK_IS_CRITICAL),
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[ZX_CLK_DDR_CTRL_WCLK] = GATE("ddr-ctrl-wclk", PARENT_ID(ZX_CLK_DDR_CTRL_MUX), 0x100, 18,
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CLK_IS_CRITICAL),
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[ZX_CLK_ZSP_PCLK] = GATE("zsp-pclk", clk_main[0], 0x34, 0, 0),
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[ZX_CLK_ZSP_WCLK] = GATE("zsp-wclk", PARENT_ID(ZX_CLK_ZSP_MUX), 0x34, 1, 0),
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/* Both SDIO controllers depend on the ahb-pclk for register access. */
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[ZX_CLK_SD0_PCLK] = GATE("sd0-pclk", PARENT_FW("ahb"), 0x54, 12, 0),
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[ZX_CLK_SD0_WCLK] = GATE("sd0-wclk", PARENT_ID(ZX_CLK_SD0_MUX), 0x54, 13, 0),
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[ZX_CLK_SD0_CDET] = GATE("sd0-cdet", PARENT_FW("osc32k"), 0x54, 14, 0),
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[ZX_CLK_SD1_PCLK] = GATE("sd1-pclk", PARENT_FW("ahb"), 0x54, 4, 0),
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[ZX_CLK_SD1_WCLK] = GATE("sd1-wclk", PARENT_ID(ZX_CLK_SD1_MUX), 0x54, 5, 0),
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/*
|
||||
* I don't know how the cdet clock works. Card detection in the way the dwc,mmc driver uses
|
||||
* it appears broken no matter this clock's setting.
|
||||
*/
|
||||
[ZX_CLK_SD1_CDET] = GATE("sd1-cdet", PARENT_FW("osc32k"), 0x54, 6, 0),
|
||||
|
||||
/* This is some "denali" NAND, not the qspi connected one */
|
||||
[ZX_CLK_NAND_WCLK] = GATE("nand-wclk", PARENT_ID(ZX_CLK_NAND_MUX), 0x54, 20, 0),
|
||||
[ZX_CLK_NAND_PCLK] = GATE("nand-pclk", clk_main[0], 0x54, 21, 0),
|
||||
|
||||
/*
|
||||
* There is a set of gates for an unknown device at matrix+0x60. It is some LTE related
|
||||
* device and the pclk gates off mmio areas 0xf8000000 and 0xfc000000. These areas are only
|
||||
* accessible to M0 and ZSP, not the AP.
|
||||
*
|
||||
* If it is fed an incorrect clock, e.g. because dpll is not locked and outputs 26 MHz, it
|
||||
* will spam IRQs at SPI 68. This is likely a distress notification that some
|
||||
* internal PLL did not lock or similar. ZTE's kernel has two defines for SPI 68:
|
||||
* "LTE_TPU_INT_PS_INT" and "VOU_OSD_INT". The latter is unlikely because VOU related clocks
|
||||
* sit in matrix+0x168.
|
||||
*
|
||||
* The address space in 0xfc000000 appears to contain a number of different devices, so I
|
||||
* have named the clock LTE_MODEM_{W/P}CLK. It is not known how this mmio area and clock
|
||||
* relates to SPI 68 or the ABB clock in topcrm+0x144. Because it is not accessible to the
|
||||
* AP at all, I don't think we need to care beyond turning on the clocks before booting the
|
||||
* ZSP.
|
||||
*
|
||||
* Bit 9 in register 0x118 turns the IRQs off, so it is the immediate wclk parent. It isn't
|
||||
* clear what divisor of dpll it is using though. Following the pattern that lower
|
||||
* frequencies are gated by lower bits, it would indicate dpll/2 or dpll/3.
|
||||
*/
|
||||
[ZX_CLK_LTE_MODEM_WCLK] = GATE("lte-modem-wclk", PARENT_ID(ZX_CLK_MATRIX_DPLL_D2),
|
||||
0x60, 0, 0),
|
||||
[ZX_CLK_LTE_MODEM_PCLK] = GATE("lte-modem-pclk", clk_main[0],
|
||||
0x60, 2, 0),
|
||||
|
||||
[ZX_CLK_EDCP_PCLK] = GATE("edcp-pclk", clk_main[0], 0x64, 1, 0),
|
||||
[ZX_CLK_EDCP_WCLK] = GATE("edcp-wclk", PARENT_ID(ZX_CLK_EDCP_MUX), 0x64, 2, 0),
|
||||
|
||||
/*
|
||||
* This seems to be another SPI-Like device. cpko.ko uses it to send calibration blobs to
|
||||
* the LTE radio hardware. After initialization the ZSP firmware takes over control of this
|
||||
* device.
|
||||
*
|
||||
* Testing reveals the parent as matrix's 104 MHz mpll fraction.
|
||||
*/
|
||||
[ZX_CLK_RFFE_WCLK] = GATE("rffe-wclk", PARENT_ID(ZX_CLK_MATRIX_MPLL_D6), 0x84, 0, 0),
|
||||
[ZX_CLK_SSC_WCLK] = GATE("ssc-wclk", PARENT_ID(ZX_CLK_MATRIX_MPLL_D6), 0x84, 1, 0),
|
||||
[ZX_CLK_SSC_PCLK] = GATE("ssc-pclk", clk_main[0], 0x84, 2, 0),
|
||||
|
||||
/*
|
||||
* PDCFG. Like PMM, either clock bit will allow the device to function. Probably there is
|
||||
* no wclk line at all and the two bits are just an artifact of generally having two bits
|
||||
* per device.
|
||||
*/
|
||||
[ZX_CLK_PDCFG_WCLK] = GATE("pdcfg-wclk", matrix_unk, 0x88, 0, CLK_IS_CRITICAL),
|
||||
[ZX_CLK_PDCFG_PCLK] = GATE("pdcfg-pclk", clk_main[0], 0x88, 1, CLK_IS_CRITICAL),
|
||||
[ZX_CLK_MBOX_PCLK] = GATE("mbox-pclk", clk_main[0], 0x88, 2, 0),
|
||||
[ZX_CLK_SRAM0_PCLK] = GATE("sram0-pclk", clk_main[0], 0x88, 4, 0),
|
||||
[ZX_CLK_GSM_CFG_PCLK] = GATE("gsm-cfg-pclk", clk_main[0], 0x88, 8, 0),
|
||||
|
||||
/*
|
||||
* ZTE's driver has a statement to the effect of *(top->base+0x11c) = 5, with a comment
|
||||
* suggesting that this sets a 50 MHz clock. The clock code itself lists GMAC clocks in
|
||||
* matrix+0x110 and lists the parents of these clocks as 50 MHz gpll output, but
|
||||
* the downstream ZTE GMAC driver never enables the clocks. It turns out ZTE's code is
|
||||
* highly misleading.
|
||||
*
|
||||
* The GMAC's work clock is definitely not any gpll output because it keeps working fine
|
||||
* with gpll disabled. Gating off matrix-osc26m breaks GMAC, so it must be its parent.
|
||||
*
|
||||
* The GMAC Gates are left enabled by the boot loader and are required for the GMAC to work.
|
||||
*
|
||||
* As for the 50 MHz comment: See rmiiphy-wclk.
|
||||
*
|
||||
* The gmac-ahb clock is a child of topcrm's ahb-pclk and is required for DMA transfers in
|
||||
* and out of GMAC. Without it, GMAC still receives ethernet frames, but can't drain them
|
||||
* to memory and will eventually set the RX FIFO overflow flag.
|
||||
*/
|
||||
[ZX_CLK_GMAC_WCLK] = GATE("gmac-wclk", PARENT_FW("wclk-osc26m"), 0x110, 0, 0),
|
||||
[ZX_CLK_GMAC_PCLK] = GATE("gmac-pclk", clk_main[0], 0x110, 1, 0),
|
||||
[ZX_CLK_GMAC_AHB] = GATE("gmac-ahb", PARENT_FW("ahb"), 0x110, 2, 0),
|
||||
|
||||
/*
|
||||
* Is there an AXI bus gate? The symptom of cutting off the AXI mux selection in top+0x140
|
||||
* is that matrixcrm becomes unreadable from m0 and A53 hangs. Inside matrix itself only 3
|
||||
* bits fit that bill: 0x8c bits 5, 6, 7. It seems a bit self-defeating to have a clock
|
||||
* gate that shuts off access to itself though. I expect a clock gate for the bus
|
||||
* somewhere, and the mux exists, so exposing one AXI clock in the bindings is the correct
|
||||
* thing to do. It also serves to tell the kernel to keep the mux's parent enabled.
|
||||
*
|
||||
* Register 0x8c has 12 settable bits (0xfff). Ultimately it doesn't matter much which
|
||||
* do-not-remove bit we don't remove. Other bits in this register behave like gates (e.g
|
||||
* bits 11:8 cut off USB temporarily), so I think we are looking in the right place.
|
||||
*
|
||||
* If an explanation for the remaining bits surfaces and they are further gates and/or
|
||||
* resets, add them to the bindings.
|
||||
*/
|
||||
[ZX_CLK_AXI_WCLK] = GATE("axi-wclk", PARENT_ID(ZX_CLK_AXI_MUX), 0x8c, 5,
|
||||
CLK_IS_CRITICAL),
|
||||
|
||||
[ZX_CLK_DMA_PCLK] = GATE("dma-pclk", clk_main[0], 0x94, 3, 0),
|
||||
|
||||
/*
|
||||
* There are a lot more VOU related controls in these registers, but turning off the main
|
||||
* clock seems to shut off the entire VOU MMIO range.
|
||||
*/
|
||||
[ZX_CLK_VOU_WCLK] = GATE("vou-wclk", matrix_unk, 0x168, 0, 0),
|
||||
[ZX_CLK_VOU_PCLK] = GATE("vou-pclk", clk_main[0], 0x168, 1, 0),
|
||||
|
||||
/*
|
||||
* LSP uplink clocks. The pclk is fairly obvious (disabling it shuts off the entire LSP
|
||||
* register area). The wclk speeds were deduced by setting timers and qspi muxes to a
|
||||
* specific speed and seeing which bit in matrix+0x7c needs to be enabled for the device
|
||||
* to work.
|
||||
*
|
||||
* Due to the timers I am certain about the 26 MHz and 32 kHz clocks. I cannot directly
|
||||
* observe the qspi mux frequency, so the clock rates depend on ZTE's qspi mux selection
|
||||
* being correct.
|
||||
*
|
||||
* Two additional bits are specific to sound components - the mux for the LSP's TDM IP is
|
||||
* in matrixcrm and gets passed down. I2S has a mux in LSP, which can select the dpll-d4
|
||||
* clock.
|
||||
*/
|
||||
[ZX_CLK_TOLSP_MPLL_D5_WCLK] = GATE("lsp-mpll-d5", PARENT_FW("mpll-d5"), 0x7c, 0, 0),
|
||||
[ZX_CLK_TOLSP_MPLL_D4_WCLK] = GATE("lsp-mpll-d4", PARENT_ID(ZX_CLK_MATRIX_MPLL_D4),
|
||||
0x7c, 1, 0),
|
||||
[ZX_CLK_TOLSP_MPLL_D6_WCLK] = GATE("lsp-mpll-d6", PARENT_ID(ZX_CLK_MATRIX_MPLL_D6),
|
||||
0x7c, 2, 0),
|
||||
[ZX_CLK_TOLSP_MPLL_D8_WCLK] = GATE("lsp-mpll-d8", PARENT_ID(ZX_CLK_MATRIX_MPLL_D8),
|
||||
0x7c, 3, 0),
|
||||
[ZX_CLK_TOLSP_MPLL_D12_WCLK] = GATE("lsp-mpll-d12", PARENT_ID(ZX_CLK_MATRIX_MPLL_D12),
|
||||
0x7c, 4, 0),
|
||||
[ZX_CLK_TOLSP_OSC26M_WCLK] = GATE("lsp-osc26m", PARENT_FW("wclk-osc26m"), 0x7c, 5, 0),
|
||||
[ZX_CLK_TOLSP_OSC32K_WCLK] = GATE("lsp-osc32k", PARENT_FW("osc32k"), 0x7c, 6, 0),
|
||||
[ZX_CLK_TOLSP_PCLK] = GATE("lsp-pclk", clk_main[0], 0x7c, 7, 0),
|
||||
[ZX_CLK_TOLSP_TDM_WCLK] = GATE("lsp-tdm-wclk", PARENT_ID(ZX_CLK_TDM_MUX), 0x7c, 8, 0),
|
||||
[ZX_CLK_TOLSP_DPLL_D4_WCLK] = GATE("lsp-dpll-d4", PARENT_ID(ZX_CLK_MATRIX_DPLL_D4),
|
||||
0x7c, 9, 0),
|
||||
};
|
||||
|
||||
static int zx297520v3_matrix_init(struct regmap *map)
|
||||
{
|
||||
u32 axi_val;
|
||||
int res;
|
||||
|
||||
/* Read the global AXI speed selection, insert it into our ballot and enable voting */
|
||||
res = regmap_read(map, 0x0, &axi_val);
|
||||
if (res)
|
||||
return res;
|
||||
|
||||
axi_val &= 0x7;
|
||||
res = regmap_write(map, ZX297520V3_AXI_AP_VOTE, axi_val);
|
||||
if (res)
|
||||
return res;
|
||||
|
||||
return regmap_write(map, 0x12c, 1);
|
||||
}
|
||||
|
||||
static const unsigned int zx297520v3_matrix_exports[] = {
|
||||
[ZX297520V3_SYS_TIMER_WCLK] = ZX_CLK_SYS_TIMER_WCLK,
|
||||
[ZX297520V3_CPU_WCLK] = ZX_CLK_CPU_WCLK,
|
||||
[ZX297520V3_CPU_PCLK] = ZX_CLK_CPU_PCLK,
|
||||
[ZX297520V3_ZSP_WCLK] = ZX_CLK_ZSP_WCLK,
|
||||
[ZX297520V3_ZSP_PCLK] = ZX_CLK_ZSP_PCLK,
|
||||
[ZX297520V3_DDR_CTRL_PCLK] = ZX_CLK_DDR_CTRL_PCLK,
|
||||
[ZX297520V3_DDR_CTRL_WCLK] = ZX_CLK_DDR_CTRL_WCLK,
|
||||
[ZX297520V3_EDCP_WCLK] = ZX_CLK_EDCP_WCLK,
|
||||
[ZX297520V3_EDCP_PCLK] = ZX_CLK_EDCP_PCLK,
|
||||
[ZX297520V3_SD0_WCLK] = ZX_CLK_SD0_WCLK,
|
||||
[ZX297520V3_SD0_PCLK] = ZX_CLK_SD0_PCLK,
|
||||
[ZX297520V3_SD0_CDET] = ZX_CLK_SD0_CDET,
|
||||
[ZX297520V3_SD1_WCLK] = ZX_CLK_SD1_WCLK,
|
||||
[ZX297520V3_SD1_PCLK] = ZX_CLK_SD1_PCLK,
|
||||
[ZX297520V3_SD1_CDET] = ZX_CLK_SD1_CDET,
|
||||
[ZX297520V3_NAND_WCLK] = ZX_CLK_NAND_WCLK,
|
||||
[ZX297520V3_NAND_PCLK] = ZX_CLK_NAND_PCLK,
|
||||
[ZX297520V3_DMA_PCLK] = ZX_CLK_DMA_PCLK,
|
||||
[ZX297520V3_MBOX_PCLK] = ZX_CLK_MBOX_PCLK,
|
||||
[ZX297520V3_PDCFG_WCLK] = ZX_CLK_PDCFG_WCLK,
|
||||
[ZX297520V3_PDCFG_PCLK] = ZX_CLK_PDCFG_PCLK,
|
||||
[ZX297520V3_RFFE_WCLK] = ZX_CLK_RFFE_WCLK,
|
||||
[ZX297520V3_SSC_WCLK] = ZX_CLK_SSC_WCLK,
|
||||
[ZX297520V3_SSC_PCLK] = ZX_CLK_SSC_PCLK,
|
||||
[ZX297520V3_AXI_WCLK] = ZX_CLK_AXI_WCLK,
|
||||
[ZX297520V3_GMAC_WCLK] = ZX_CLK_GMAC_WCLK,
|
||||
[ZX297520V3_GMAC_PCLK] = ZX_CLK_GMAC_PCLK,
|
||||
[ZX297520V3_GMAC_AHB] = ZX_CLK_GMAC_AHB,
|
||||
[ZX297520V3_VOU_WCLK] = ZX_CLK_VOU_WCLK,
|
||||
[ZX297520V3_VOU_PCLK] = ZX_CLK_VOU_PCLK,
|
||||
[ZX297520V3_LSP_MPLL_D5_WCLK] = ZX_CLK_TOLSP_MPLL_D5_WCLK,
|
||||
[ZX297520V3_LSP_MPLL_D4_WCLK] = ZX_CLK_TOLSP_MPLL_D4_WCLK,
|
||||
[ZX297520V3_LSP_MPLL_D6_WCLK] = ZX_CLK_TOLSP_MPLL_D6_WCLK,
|
||||
[ZX297520V3_LSP_MPLL_D8_WCLK] = ZX_CLK_TOLSP_MPLL_D8_WCLK,
|
||||
[ZX297520V3_LSP_MPLL_D12_WCLK] = ZX_CLK_TOLSP_MPLL_D12_WCLK,
|
||||
[ZX297520V3_LSP_OSC26M_WCLK] = ZX_CLK_TOLSP_OSC26M_WCLK,
|
||||
[ZX297520V3_LSP_OSC32K_WCLK] = ZX_CLK_TOLSP_OSC32K_WCLK,
|
||||
[ZX297520V3_LSP_PCLK] = ZX_CLK_TOLSP_PCLK,
|
||||
[ZX297520V3_LSP_TDM_WCLK] = ZX_CLK_TOLSP_TDM_WCLK,
|
||||
[ZX297520V3_LSP_DPLL_D4_WCLK] = ZX_CLK_TOLSP_DPLL_D4_WCLK,
|
||||
[ZX297520V3_SRAM0_PCLK] = ZX_CLK_SRAM0_PCLK,
|
||||
[ZX297520V3_GSM_CFG_PCLK] = ZX_CLK_GSM_CFG_PCLK,
|
||||
[ZX297520V3_LTE_MODEM_WCLK] = ZX_CLK_LTE_MODEM_WCLK,
|
||||
[ZX297520V3_LTE_MODEM_PCLK] = ZX_CLK_LTE_MODEM_PCLK,
|
||||
};
|
||||
|
||||
static const struct zx_clk_data zx297520v3_matrixclk_data = {
|
||||
.init = zx297520v3_matrix_init,
|
||||
.clocks = zx297520v3_matrix_clocks,
|
||||
.num_clocks = ARRAY_SIZE(zx297520v3_matrix_clocks),
|
||||
.exports = zx297520v3_matrix_exports,
|
||||
.num_exports = ARRAY_SIZE(zx297520v3_matrix_exports),
|
||||
};
|
||||
|
||||
static int clk_zx297520v3_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct platform_device_id *id = platform_get_device_id(pdev);
|
||||
|
|
@ -828,6 +1350,10 @@ static const struct platform_device_id clk_zx297520v3_ids[] = {
|
|||
.name = "zx297520v3-topclk",
|
||||
.driver_data = (kernel_ulong_t)&zx297520v3_topclk_data,
|
||||
},
|
||||
{
|
||||
.name = "zx297520v3-matrixclk",
|
||||
.driver_data = (kernel_ulong_t)&zx297520v3_matrixclk_data,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, clk_zx297520v3_ids);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user