From 6f0b0c03fb97596ca313435df8e5d3fc52e8d00c Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 2 May 2017 10:03:01 +0200 Subject: [PATCH 01/13] ARM: dts: omap4-droid4: Add isl29030 ALS/proximity sensor The Droid 4 has a isl29030 to measure ambient light (e.g. for automatically adapting display brightness) and proximity. Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 13f8d8640208..935af4e8b33c 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -348,6 +348,17 @@ tsp@4a { interrupt-names = "irq", "wakeup"; wakeup-source; }; + + isl29030@44 { + compatible = "isil,isl29030"; + reg = <0x44>; + + pinctrl-names = "default"; + pinctrl-0 = <&als_proximity_pins>; + + interrupt-parent = <&gpio6>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */ + }; }; &omap4_pmx_core { @@ -395,6 +406,12 @@ OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3) >; }; + als_proximity_pins: pinmux_als_proximity_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + usb_ulpi_pins: pinmux_usb_ulpi_pins { pinctrl-single,pins = < OMAP4_IOPAD(0x196, MUX_MODE7) From d809f2cca354d88ccc19aad1ecbe54704448615e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 8 Jun 2017 23:16:08 +0200 Subject: [PATCH 02/13] ARM: dts: omap4-droid4: Fix WLAN compatible Motorola Droid 4 uses a WL1285C, so use proper compatible value. To avoid regressions while support for the new compatible value is added to the Linux kernel, the old compatible value is preserved as fallback. Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 935af4e8b33c..10ca1c174995 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -301,7 +301,7 @@ &mmc3 { #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { - compatible = "ti,wl1283"; + compatible = "ti,wl1285", "ti,wl1283"; reg = <2>; interrupt-parent = <&gpio4>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */ From c8ceb5ac1ac0aa9bd7c2be9c094f58672bd5669a Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Jun 2017 16:27:25 -0500 Subject: [PATCH 03/13] ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers M4 & M5 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP100 values as defined in the OMAP4430 ES2.x Public TRM vAP, section "3.6.3.8.7 DPLL_IVA Preferred Settings". The DPLL locked frequency is 1862.4 MHz (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap44xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 9573b37fbaa7..9cb205b87835 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -357,6 +357,8 @@ dpll_iva_ck: dpll_iva_ck@1a0 { compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <931200000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { @@ -374,6 +376,8 @@ dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { reg = <0x01b8>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m4x2_ck>; + assigned-clock-rates = <465600000>; }; dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { @@ -385,6 +389,8 @@ dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { reg = <0x01bc>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m5x2_ck>; + assigned-clock-rates = <266100000>; }; dpll_mpu_ck: dpll_mpu_ck@160 { From b58104f0a66c70b4bee271881d4496dfdec194c2 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Jun 2017 16:27:26 -0500 Subject: [PATCH 04/13] ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers H11 & H12 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP_NOM values as defined in the OMAP5432 SR2.0 Data Manual Book vK, section 5.2.3.5 "DPLL_IVA Preferred Settings". The recommended maximum DPLL locked frequency is 2330 MHz for OPP_NOM (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. The value 465.92 MHz is used instead of 465.9 MHz for dpll_iva_h11x2_ck so that proper divider value can be calculated. Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 4899c2359d0a..529193442620 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -315,6 +315,8 @@ dpll_iva_ck: dpll_iva_ck@1a0 { compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { @@ -330,6 +332,8 @@ dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { ti,max-div = <63>; reg = <0x01b8>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h11x2_ck>; + assigned-clock-rates = <465920000>; }; dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { @@ -339,6 +343,8 @@ dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { ti,max-div = <63>; reg = <0x01bc>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h12x2_ck>; + assigned-clock-rates = <388300000>; }; mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { From 39879c7d963ef6392235b2cc107c2d6dd25aa55d Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Jun 2017 16:27:27 -0500 Subject: [PATCH 05/13] ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL The IPU1 functional clock is actually the output of a mux clock, ipu1_gfclk_mux. The mux clock is sourced by default from the DPLL_ABE_X2_CLK, and this results in a rather odd clock frequency (361 MHz) for the IPU1 functional clock on platforms where ABE_DPLL is configured properly. Reconfigure the mux clock to be sourced from CORE_IPU_ISS_BOOST_CLK (dpll_core_h22x2_ck), so that both the IPU1 and IPU2 are running from the same clock and clocked at the same nominal frequency of 425 MHz. This also ensures that IPU1 functional clock is always configured properly and becomes independent of the state of the ABE DPLL on all boards. Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3330738e4c6e..cfaf27215901 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -791,6 +791,8 @@ ipu1_gfclk_mux: ipu1_gfclk_mux@520 { clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; ti,bit-shift = <24>; reg = <0x0520>; + assigned-clocks = <&ipu1_gfclk_mux>; + assigned-clock-parents = <&dpll_core_h22x2_ck>; }; mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 { From 268f6644aa0c2d73bfcebf0e3f0ffc9fc82f82cd Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Jun 2017 16:27:28 -0500 Subject: [PATCH 06/13] ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates The DSP DPLL is a new DPLL compared to previous OMAP generations and supplies the root clocks for the DSP processors, as well as a mux input source for EVE sub-system (on applicable SoCs). This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the DSP DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The DSP DPLL provides two output clocks, DSP_GFCLK and EVE_GCLK. The desired rate for DSP_GFCLK is 600 MHz (same as DSP DPLL CLKOUT frequency), and is currently auto set due to the desired M2 divider value being the same as reset value for the locked frequency of 600 MHz. The EVE_GCLK however is required to be 400 MHz, so set the dpll_dsp_m3x2_ck's rate explicitly so that the divider is set properly. The dpll_dsp_m2_ck rate is also set explicitly to not rely on any implicit matching divider reset values to the locked DPLL frequency. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 1200 MHz, so the dpll_dsp_ck clock rate used is half of this value. Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfaf27215901..8a82490035d9 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -338,6 +338,8 @@ dpll_dsp_ck: dpll_dsp_ck@234 { compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; + assigned-clocks = <&dpll_dsp_ck>; + assigned-clock-rates = <600000000>; }; dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { @@ -349,6 +351,8 @@ dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { reg = <0x0244>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m2_ck>; + assigned-clock-rates = <600000000>; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { @@ -659,6 +663,8 @@ dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { reg = <0x0248>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m3x2_ck>; + assigned-clock-rates = <400000000>; }; dpll_gmac_x2_ck: dpll_gmac_x2_ck { From 32a04832a120b8ddc6b8752d30ba4be00fa23b74 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 7 Jun 2017 16:27:29 -0500 Subject: [PATCH 07/13] ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates The IVA DPLL in DRA7xx provides the output clocks for only the IVAHD subsystem in DRA7xx as compared to previous OMAP generations when it provided the clocks for both DSP and IVAHD subsystems. This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset value of the divider M2 (that supplies the IVA_GFLCK, the functional clock for the IVAHD subsystem) does not match a specific OPP. So, the derived output clock from this IVA DPLL has to be initialized as well to avoid initializing these divider outputs to an incorrect frequencies. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 2300 MHz, so the dpll_iva_ck clock rate used is half of this value. The value for the divider clock, dpll_iva_m2_ck, has to be set to 388.333334 MHz or more for the divider clk logic to compute the appropriate divider value for OPP_NOM. Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 8a82490035d9..76e2b7478141 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -376,6 +376,8 @@ dpll_iva_ck: dpll_iva_ck@1a0 { compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { @@ -387,6 +389,8 @@ dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { reg = <0x01b0>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m2_ck>; + assigned-clock-rates = <388333334>; }; iva_dclk: iva_dclk { From fcd104b50fd0a8b638ab01b2e17252d16868aa49 Mon Sep 17 00:00:00 2001 From: Subhajit Paul Date: Wed, 7 Jun 2017 16:27:30 -0500 Subject: [PATCH 08/13] ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocks The GPU has two functional clocks - GPU_CORE_GCLK and GPU_HYD_GCLK. Both of these are mux clocks and are derived from the DPLL_CORE H14 output clock CORE_GPU_CLK by default. These clocks can also be be derived from DPLL_PER or DPLL_GPU. The GPU DPLL provides the output clocks primarily for the GPU. Configuring the GPU for different OPP clock frequencies is easier to achieve when using the DPLL_GPU rather than the other two DPLLs due to: 1. minimal affect on any other output clocks from these DPLLs 2. may require an impossible post-divider values on existing DPLLs without affecting other clocks. So, switch the GPU functional clocks to be sourced from GPU DPLL by default. This is done using the DT standard properties "assigned-clocks" and "assigned-clock-parents". Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration as all the required ABB/AVS setup is performed within the bootloader. Note that there is no DVFS supported for any of the non-MPU domains. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. This patch also sets the initial values for the DPLL_GPU outputs. These values are chosen based on the OPP_NOM values defined as per recommendation from design team. The DPLL locked frequency is kept at 1277 MHz, so that the value for the divider clock, dpll_gpu_m2_ck, can be set to 425.67 MHz for OPP_NOM. Signed-off-by: Subhajit Paul [s-anna@ti.com: revise patch description] Signed-off-by: Suman Anna Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 76e2b7478141..cf229dfabf61 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -414,6 +414,8 @@ dpll_gpu_ck: dpll_gpu_ck@2d8 { compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; + assigned-clocks = <&dpll_gpu_ck>; + assigned-clock-rates = <1277000000>; }; dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { @@ -425,6 +427,8 @@ dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { reg = <0x02e8>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_gpu_m2_ck>; + assigned-clock-rates = <425666667>; }; dpll_core_m2_ck: dpll_core_m2_ck@130 { @@ -1760,6 +1764,8 @@ gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <24>; reg = <0x1220>; + assigned-clocks = <&gpu_core_gclk_mux>; + assigned-clock-parents = <&dpll_gpu_m2_ck>; }; gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { @@ -1768,6 +1774,8 @@ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <26>; reg = <0x1220>; + assigned-clocks = <&gpu_hyd_gclk_mux>; + assigned-clock-parents = <&dpll_gpu_m2_ck>; }; l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { From c3d28e537999bc7c7d39ca09d11252137e1fee02 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 1 Jun 2017 07:26:37 -0700 Subject: [PATCH 09/13] ARM: dts: omap4-droid4: Configure CPCAP battery driver Configure CPCAP battery driver. Cc: devicetree@vger.kernel.org Cc: Marcel Partap Cc: Michael Scott Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi index f5aeb3959afd..1eb5da1dc8f0 100644 --- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi +++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi @@ -26,6 +26,22 @@ cpcap_adc: adc { #io-channel-cells = <1>; }; + cpcap_battery: battery { + compatible = "motorola,cpcap-battery"; + interrupts-extended = < + &cpcap 6 0 &cpcap 5 0 &cpcap 3 0 + &cpcap 20 0 &cpcap 54 0 + >; + interrupt-names = + "eol", "lowbph", "lowbpl", + "chrgcurr1", "battdetb"; + io-channels = <&cpcap_adc 0 &cpcap_adc 1 + &cpcap_adc 5 &cpcap_adc 6>; + io-channel-names = "battdetb", "battp", + "chg_isense", "batti"; + power-supplies = <&cpcap_charger>; + }; + cpcap_charger: charger { compatible = "motorola,mapphone-cpcap-charger"; interrupts-extended = < From 25e6cfc81a352a5e85aa8a26972d453c4c121ad1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 13 Jun 2017 11:28:43 +0200 Subject: [PATCH 10/13] ARM: dts: omap4: Fix aes entry OMAP4 has a second aes module, so let's use proper name for the first instance. Signed-off-by: Sebastian Reichel Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 578c53f08309..589690e034d3 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -900,9 +900,9 @@ usb_otg_hs: usb_otg_hs@4a0ab000 { ctrl-module = <&omap_control_usbotg>; }; - aes: aes@4b501000 { + aes1: aes@4b501000 { compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; + ti,hwmods = "aes1"; reg = <0x4b501000 0xa0>; interrupts = ; dmas = <&sdma 111>, <&sdma 110>; From 7ca3e39719aafb1b9eaf282102574f26d52acd95 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 13 Jun 2017 11:28:44 +0200 Subject: [PATCH 11/13] ARM: dts: omap4.dtsi: remove aes[12]_fck "aes1_fck" and "aes2_fck" are controlled by hwmod. Drop clock entries to avoid conflicts. Signed-off-by: Sebastian Reichel Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap44xx-clocks.dtsi | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 9cb205b87835..05732ed4f50f 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -975,22 +975,6 @@ per_abe_nc_fclk: per_abe_nc_fclk@108 { ti,max-div = <2>; }; - aes1_fck: aes1_fck@15a0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x15a0>; - }; - - aes2_fck: aes2_fck@15a8 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x15a8>; - }; - dss_sys_clk: dss_sys_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; From c6faccf21caffc433217f0fa58b8ef5c5e318a5d Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 13 Jun 2017 16:45:48 +0300 Subject: [PATCH 12/13] ARM: dts: omap4: add aes2 instance OMAP4 has AES2 instance, so add its integration data under DT. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 589690e034d3..00e7656e0856 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -909,6 +909,15 @@ aes1: aes@4b501000 { dma-names = "tx", "rx"; }; + aes2: aes@4b701000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes2"; + reg = <0x4b701000 0xa0>; + interrupts = ; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; + des: des@480a5000 { compatible = "ti,omap4-des"; ti,hwmods = "des"; From 45f1d5e3c71d479995cefe9dd30344c62efd60c8 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 13 Jun 2017 16:45:49 +0300 Subject: [PATCH 13/13] ARM: dts: omap4: add SHAM node Add SHAM crypto accelerator. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 00e7656e0856..64d00f5893a6 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -927,6 +927,15 @@ des: des@480a5000 { dma-names = "tx", "rx"; }; + sham: sham@4b100000 { + compatible = "ti,omap4-sham"; + ti,hwmods = "sham"; + reg = <0x4b100000 0x300>; + interrupts = ; + dmas = <&sdma 119>; + dma-names = "rx"; + }; + abb_mpu: regulator-abb-mpu { compatible = "ti,abb-v2"; regulator-name = "abb_mpu";