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fix DLL off bug, fix ZQCR[1] bug, add to support change BL, add dsb()
This commit is contained in:
hcy
parent
7c31576136
commit
0d54b690bb
117
arch/arm/mach-rk30/ddr.c
Normal file → Executable file
117
arch/arm/mach-rk30/ddr.c
Normal file → Executable file
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@ -124,7 +124,7 @@ typedef uint32_t uint32;
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//mr1 for ddr3
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#define DDR3_DLL_ENABLE (0)
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#define DDR3_DLL_DISABLE (1)
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#define DDR3_MR1_AL(n) (((n)&0x7)<<3)
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#define DDR3_MR1_AL(n) (((n)&0x3)<<3)
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#define DDR3_DS_40 (0)
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#define DDR3_DS_34 (1<<1)
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@ -914,11 +914,11 @@ DDR_CONFIG_2_RBC_T ddr_cfg_2_rbc[16] =
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{15,3,10} // bank ahead
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};
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uint32_t ddr_data_training_buf[32];
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__attribute__((aligned(4096))) uint32_t ddr_data_training_buf[32];
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uint32_t __sramdata ddr3_cl_cwl[22][4]={
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/* 0~330 330~400 400~533 speed
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* tCK >3 2.5~3 1.875~2.5 1.875~1.5
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* tCK >3 2.5~3 1.875~2.5 1.5~1.875
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* cl<<16, cwl cl<<16, cwl cl<<16, cwl */
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{((5<<16)|5), ((5<<16)|5), 0 , 0}, //DDR3_800D
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{((5<<16)|5), ((6<<16)|5), 0 , 0}, //DDR3_800E
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@ -929,7 +929,7 @@ uint32_t __sramdata ddr3_cl_cwl[22][4]={
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{((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_1333F
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{((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((8<<16)|7)}, //DDR3_1333G
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{((5<<16)|5), ((6<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_1333H
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{((5<<16)|5), ((6<<16)|5), ((8<<16)|6), ((9<<16)|7)}, //DDR3_1333H
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{((5<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)}, //DDR3_1333J
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{((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_1600G
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@ -993,13 +993,13 @@ Cpu highest frequency is 1.6 GHz
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1 cycle = 1/1.6 ns
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1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
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*****************************************************************************/
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static __sramdata uint32_t loops_per_us;
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static __sramdata volatile uint32_t loops_per_us;
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#define LPJ_100MHZ 999456UL
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/*static*/ void __sramlocalfunc ddr_delayus(uint32_t us)
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{
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uint32_t count;
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volatile uint32_t count;
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count = loops_per_us*us;
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while(count--) // 3 cycles
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@ -1115,12 +1115,15 @@ __sramfunc void ddr_move_to_Lowpower_state(void)
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{
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case Init_mem:
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pDDR_Reg->SCTL = CFG_STATE;
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dsb();
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while((pDDR_Reg->STAT.b.ctl_stat) != Config);
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case Config:
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pDDR_Reg->SCTL = GO_STATE;
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dsb();
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while((pDDR_Reg->STAT.b.ctl_stat) != Access);
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case Access:
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pDDR_Reg->SCTL = SLEEP_STATE;
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dsb();
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while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
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break;
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default: //Transitional state
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@ -1135,6 +1138,7 @@ __sramfunc void ddr_move_to_Access_state(void)
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//set auto self-refresh idle
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pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)|ddr_sr_idle;
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dsb();
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while(1)
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{
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@ -1148,14 +1152,17 @@ __sramfunc void ddr_move_to_Access_state(void)
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{
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case Low_power:
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pDDR_Reg->SCTL = WAKEUP_STATE;
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dsb();
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while((pDDR_Reg->STAT.b.ctl_stat) != Access);
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while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
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break;
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case Init_mem:
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pDDR_Reg->SCTL = CFG_STATE;
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dsb();
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while((pDDR_Reg->STAT.b.ctl_stat) != Config);
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case Config:
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pDDR_Reg->SCTL = GO_STATE;
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dsb();
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while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
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|| ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
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break;
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@ -1187,11 +1194,13 @@ __sramfunc void ddr_move_to_Config_state(void)
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{
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case Low_power:
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pDDR_Reg->SCTL = WAKEUP_STATE;
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dsb();
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while((pDDR_Reg->STAT.b.ctl_stat) != Access);
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while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
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case Access:
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case Init_mem:
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pDDR_Reg->SCTL = CFG_STATE;
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dsb();
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while((pDDR_Reg->STAT.b.ctl_stat) != Config);
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break;
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default: //Transitional state
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@ -1203,9 +1212,8 @@ __sramfunc void ddr_move_to_Config_state(void)
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//arg°üÀ¨bank_addrºÍcmd_addr
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void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
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{
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uint32 i;
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pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
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for (i = 0; i < 10; i ++) {;}
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dsb();
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while(pDDR_Reg->MCMD & start_cmd);
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}
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@ -1214,17 +1222,18 @@ void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
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//!0 DTTʧ°Ü
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uint32_t __sramlocalfunc ddr_data_training(void)
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{
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uint32 i,value,cs;
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uint32 value,cs;
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// disable auto refresh
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value = pDDR_Reg->TREFI;
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pDDR_Reg->TREFI = 0;
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dsb();
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// clear DTDONE status
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pPHY_Reg->PIR |= CLRSR;
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cs = ((pPHY_Reg->PGCR>>18) & 0xF);
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// trigger DTT
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pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
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for (i = 0; i < 10; i ++) {;}
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dsb();
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// wait echo byte DTDONE
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while((pPHY_Reg->DATX8[0].DXGSR[0] & cs) != cs);
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while((pPHY_Reg->DATX8[1].DXGSR[0] & cs) != cs);
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@ -1343,14 +1352,14 @@ uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
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else
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{
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pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
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dsb();
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pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET;
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pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR(clkr) | NO(clkod);
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pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF(clkf);
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pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
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ddr_delayus(1);
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pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET;
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dsb();
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while (delay > 0)
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{
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ddr_delayus(1);
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@ -1364,6 +1373,7 @@ uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
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| 0; //clk_ddr_src:clk_ddrphy = 1:1
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pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
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dsb();
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}
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out:
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return ret;
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@ -1374,7 +1384,7 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
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uint32_t tmp;
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uint32_t ret = 0;
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uint32_t al;
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uint32_t bl;
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uint32_t bl,bl_tmp;
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uint32_t cl;
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uint32_t cwl;
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PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
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@ -1561,7 +1571,8 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
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tmp = tmp - 4;
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else
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tmp = tmp>>1;
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p_publ_timing->mr[0] = DDR3_BL8 | DDR3_CL(cl) | DDR3_WR(tmp);
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bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
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p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
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/*
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* tWTR, max(4 tCK,7.5ns)
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@ -1901,7 +1912,8 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
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* tWR, 15ns
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*/
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p_pctl_timing->twr = ((LPDDR2_tWR*nMHz+999)/1000)&0x1F;
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p_publ_timing->mr[1] = LPDDR2_BL8 | LPDDR2_nWR(((LPDDR2_tWR*nMHz+999)/1000));
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bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
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p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(((LPDDR2_tWR*nMHz+999)/1000));
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/*
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* tWTR, 7.5ns(533-266MHz) 10ns(200-166MHz)
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*/
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@ -2194,7 +2206,8 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
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*/
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tmp = ((DDR2_tWR*nMHz+999)/1000);
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p_pctl_timing->twr = tmp&0x1F;
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p_publ_timing->mr[0] = DDR2_BL4 | DDR2_CL(cl) | DDR2_WR(tmp);
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bl_tmp = (bl == 8) ? DDR2_BL8 : DDR2_BL4;
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p_publ_timing->mr[0] = bl_tmp | DDR2_CL(cl) | DDR2_WR(tmp);
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/*
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* tWTR, 10ns(200MHz) 7.5ns(>200MHz)
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*/
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@ -2360,7 +2373,8 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
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*/
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cl = 3;
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cwl = 1;
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p_publ_timing->mr[0] = mDDR_BL4 | mDDR_CL(cl);
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bl_tmp = (bl == 8) ? mDDR_BL8 : ((bl == 4) ? mDDR_BL4 : mDDR_BL2);
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p_publ_timing->mr[0] = bl_tmp | mDDR_CL(cl);
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p_publ_timing->mr[2] = mDDR_DS_3_4; //mr[2] is mDDR MR1
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p_publ_timing->mr[1] = 0;
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p_publ_timing->mr[3] = 0;
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@ -2596,7 +2610,7 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
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uint32_t __sramlocalfunc ddr_update_timing(void)
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{
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uint32_t i;
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uint32_t i,bl_tmp;
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PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
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PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
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NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
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@ -2607,15 +2621,28 @@ uint32_t __sramlocalfunc ddr_update_timing(void)
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// Update PCTL BL
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if(mem_type == DDR3)
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{
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pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | ddr2_ddr3_bl_8 | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
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bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
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pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
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pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-2;
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pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL-1;
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}
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else if(mem_type == LPDDR2)
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{
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switch(p_publ_timing->mr[1] & 0x7)
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{
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case LPDDR2_BL4:
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bl_tmp = mddr_lpddr2_bl_4;
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break;
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case LPDDR2_BL8:
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bl_tmp = mddr_lpddr2_bl_8;
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break;
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case LPDDR2_BL16:
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bl_tmp = mddr_lpddr2_bl_16;
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break;
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}
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if(ddr_freq>=200)
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{
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pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | mddr_lpddr2_bl_8 | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
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pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
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}
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else
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{
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@ -2628,11 +2655,24 @@ uint32_t __sramlocalfunc ddr_update_timing(void)
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}
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else if(mem_type == DDR2)
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{
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pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | ddr2_ddr3_bl_8 | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
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bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR2_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
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pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
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}
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else// if(mem_type == LPDDR)
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{
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pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | mddr_lpddr2_bl_4 | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
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switch(p_publ_timing->mr[0] & 0x7)
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{
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case mDDR_BL2:
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bl_tmp = mddr_lpddr2_bl_2;
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break;
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case mDDR_BL4:
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bl_tmp = mddr_lpddr2_bl_4;
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break;
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case mDDR_BL8:
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bl_tmp = mddr_lpddr2_bl_8;
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break;
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}
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pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
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}
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return 0;
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}
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@ -2640,15 +2680,16 @@ uint32_t __sramlocalfunc ddr_update_timing(void)
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uint32_t __sramlocalfunc ddr_update_mr(void)
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{
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PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
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uint32_t cs;
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uint32_t cs,dll_off;
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cs = ((pPHY_Reg->PGCR>>18) & 0xF);
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dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
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ddr_copy((uint32_t *)&(pPHY_Reg->MR[0]), (uint32_t*)&(p_publ_timing->mr[0]), 4);
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if((mem_type == DDR3) || (mem_type == DDR2))
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{
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if(ddr_freq>DDR3_DDR2_DLL_DISABLE_FREQ)
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{
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if(pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) // off -> on
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if(dll_off) // off -> on
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{
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ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((uint8_t)(p_publ_timing->mr[1]))); //DLL enable
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ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((uint8_t)(p_publ_timing->mr[0]))| DDR3_DLL_RESET)); //DLL reset
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@ -2716,9 +2757,11 @@ void __sramlocalfunc ddr_update_odt(void)
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cs = ((pPHY_Reg->PGCR>>18) & 0xF);
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if(cs > 1)
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{
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pPHY_Reg->ZQ1CR[0] = tmp;
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pPHY_Reg->ZQ1CR[1] = tmp;
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dsb();
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}
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pPHY_Reg->ZQ0CR[0] = tmp;
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dsb();
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}
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__sramfunc void ddr_adjust_config(uint32_t dram_type)
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@ -2736,6 +2779,7 @@ __sramfunc void ddr_adjust_config(uint32_t dram_type)
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flush_cache_all();
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outer_flush_all();
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flush_tlb_all();
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isb();
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DDR_SAVE_SP(save_sp);
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for(i=0;i<16;i++)
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@ -2796,30 +2840,35 @@ void __sramlocalfunc idle_port(void)
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if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
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{
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pPMU_Reg->PMU_MISC_CON1 |= idle_req_cpu_cfg;
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dsb();
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while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) == 0 );
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}
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if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
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{
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pPMU_Reg->PMU_MISC_CON1 |= idle_req_peri_cfg;
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dsb();
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while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) == 0 );
|
||||
}
|
||||
|
||||
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
|
||||
{
|
||||
pPMU_Reg->PMU_MISC_CON1 |= idle_req_vio_cfg;
|
||||
dsb();
|
||||
while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) == 0 );
|
||||
}
|
||||
|
||||
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
|
||||
{
|
||||
pPMU_Reg->PMU_MISC_CON1 |= idle_req_video_cfg;
|
||||
dsb();
|
||||
while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) == 0 );
|
||||
}
|
||||
|
||||
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
|
||||
{
|
||||
pPMU_Reg->PMU_MISC_CON1 |= idle_req_gpu_cfg;
|
||||
dsb();
|
||||
while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) == 0 );
|
||||
}
|
||||
|
||||
|
|
@ -2844,29 +2893,34 @@ void __sramlocalfunc deidle_port(void)
|
|||
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
|
||||
{
|
||||
pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_cpu_cfg;
|
||||
dsb();
|
||||
while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) != 0 );
|
||||
}
|
||||
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
|
||||
{
|
||||
pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_peri_cfg;
|
||||
dsb();
|
||||
while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) != 0 );
|
||||
}
|
||||
|
||||
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
|
||||
{
|
||||
pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_vio_cfg;
|
||||
dsb();
|
||||
while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) != 0 );
|
||||
}
|
||||
|
||||
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
|
||||
{
|
||||
pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_video_cfg;
|
||||
dsb();
|
||||
while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) != 0 );
|
||||
}
|
||||
|
||||
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
|
||||
{
|
||||
pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_gpu_cfg;
|
||||
dsb();
|
||||
while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) != 0 );
|
||||
}
|
||||
|
||||
|
|
@ -2948,6 +3002,7 @@ uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
|
|||
flush_cache_all();
|
||||
outer_flush_all();
|
||||
flush_tlb_all();
|
||||
isb();
|
||||
DDR_SAVE_SP(save_sp);
|
||||
for(i=0;i<16;i++)
|
||||
{
|
||||
|
|
@ -2997,10 +3052,10 @@ void __sramfunc ddr_suspend(void)
|
|||
volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
|
||||
|
||||
/** 1. Make sure there is no host access */
|
||||
flush_cache_all();
|
||||
outer_flush_all();
|
||||
flush_tlb_all();
|
||||
|
||||
//flush_cache_all();
|
||||
//outer_flush_all();
|
||||
//flush_tlb_all();
|
||||
|
||||
for(i=0;i<16;i++)
|
||||
{
|
||||
n=temp[1024*i];
|
||||
|
|
@ -3170,7 +3225,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
|
|||
uint32_t cs,die=1;
|
||||
uint32_t gsr,dqstr;
|
||||
|
||||
ddr_print("version 1.00 20120608 \n");
|
||||
ddr_print("version 1.00 20120820 \n");
|
||||
|
||||
mem_type = pPHY_Reg->DCR.b.DDRMD;
|
||||
ddr_speed_bin = dram_speed_bin;
|
||||
|
|
@ -3228,7 +3283,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
|
|||
gsr = pPHY_Reg->DATX8[value].DXGSR[0];
|
||||
dqstr = pPHY_Reg->DATX8[value].DXDQSTR;
|
||||
ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=0x%x, DGSL=%d extra clock, DGPS=%d\n", \
|
||||
(gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), ((gsr>>13)&0xFFF), (dqstr&0x7), (((dqstr>>12)&0x3)*90));
|
||||
(gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), ((gsr>>13)&0xFFF), (dqstr&0x7), ((((dqstr>>12)&0x3)+1)*90));
|
||||
}
|
||||
ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
|
||||
(pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user