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dpll: add DPLL_PIN_TYPE_INT_NCO pin type

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Add DPLL_PIN_TYPE_INT_NCO pin type for virtual pins representing
the NCO mode of a DPLL. When connected as a DPLL input, the DPLL
enters NCO mode where the output frequency is adjusted by the host
via the PTP clock interface.

Update the fractional-frequency-offset and fractional-frequency-
offset-ppt attribute documentation to note that for INT_NCO pins
these attributes represent the DPLL's current output frequency
offset from its nominal frequency.

Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Link: https://patch.msgid.link/20260630125536.720717-3-ivecera@redhat.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Ivan Vecera 2026-06-30 14:55:33 +02:00 committed by Paolo Abeni
parent b1d0c41208
commit 0cc8348a97
3 changed files with 18 additions and 1 deletions
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13
Documentation/netlink/specs/dpll.yaml
View File

@ -165,6 +165,13 @@ definitions:
-
name: gnss
doc: GNSS recovered clock
-
name: int-nco
doc: |
Device internal numerically controlled oscillator.
When connected as a DPLL input, the DPLL enters NCO mode
where the output frequency is adjusted by the host via
the PTP clock interface.
render-max: true
-
type: enum
@ -462,6 +469,9 @@ attribute-sets:
offset on the media associated with the pin. Inside
the pin-parent-device nest it represents the frequency
offset between the pin and its parent DPLL device.
For pins of type PIN_TYPE_INT_NCO this represents
the DPLL's current output frequency offset from its
nominal frequency.
Value is in PPM (parts per million).
This is a lower-precision version of
fractional-frequency-offset-ppt.
@ -508,6 +518,9 @@ attribute-sets:
offset on the media associated with the pin. Inside
the pin-parent-device nest it represents the frequency
offset between the pin and its parent DPLL device.
For pins of type PIN_TYPE_INT_NCO this represents
the DPLL's current output frequency offset from its
nominal frequency.
Value is in PPT (parts per trillion, 10^-12).
This is a higher-precision version of
fractional-frequency-offset.

2
drivers/dpll/dpll_nl.c
View File

@ -61,7 +61,7 @@ static const struct nla_policy dpll_pin_id_get_nl_policy[DPLL_A_PIN_TYPE + 1] =
[DPLL_A_PIN_BOARD_LABEL] = { .type = NLA_NUL_STRING, },
[DPLL_A_PIN_PANEL_LABEL] = { .type = NLA_NUL_STRING, },
[DPLL_A_PIN_PACKAGE_LABEL] = { .type = NLA_NUL_STRING, },
[DPLL_A_PIN_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 5),
[DPLL_A_PIN_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 6),
};
/* DPLL_CMD_PIN_GET - do */

4
include/uapi/linux/dpll.h
View File

@ -129,6 +129,9 @@ enum dpll_type {
* @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock
* @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator
* @DPLL_PIN_TYPE_GNSS: GNSS recovered clock
* @DPLL_PIN_TYPE_INT_NCO: Device internal numerically controlled oscillator.
* When connected as a DPLL input, the DPLL enters NCO mode where the output
* frequency is adjusted by the host via the PTP clock interface.
*/
enum dpll_pin_type {
DPLL_PIN_TYPE_MUX = 1,
@ -136,6 +139,7 @@ enum dpll_pin_type {
DPLL_PIN_TYPE_SYNCE_ETH_PORT,
DPLL_PIN_TYPE_INT_OSCILLATOR,
DPLL_PIN_TYPE_GNSS,
DPLL_PIN_TYPE_INT_NCO,
/* private: */
__DPLL_PIN_TYPE_MAX,