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drm/amdkfd: refactor rlc/gfx spm

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for adding multiple xcc support.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Bing Ma <Bing.Ma@amd.com>
Reviewed-by: Gang Ba <gaba@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu 2024-10-11 13:40:42 -04:00 committed by Alex Deucher
parent 36b266bd3a
commit 0bebe9b9fc
9 changed files with 24 additions and 17 deletions
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3
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
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@ -257,7 +257,8 @@ struct amdgpu_rlc_funcs {
void (*stop)(struct amdgpu_device *adev);
void (*reset)(struct amdgpu_device *adev);
void (*start)(struct amdgpu_device *adev);
void (*update_spm_vmid)(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid);
void (*update_spm_vmid)(struct amdgpu_device *adev, int xcc_id,
struct amdgpu_ring *ring, unsigned vmid);
bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
};

2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
View File

@ -834,7 +834,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid);
adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring, job->vmid);
if (ring->funcs->emit_gds_switch &&
gds_switch_needed) {

3
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
View File

@ -8318,7 +8318,8 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
}
}
static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
struct amdgpu_ring *ring, unsigned int vmid)
{
amdgpu_gfx_off_ctrl(adev, false);

5
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View File

@ -918,7 +918,7 @@ static int gfx_v11_0_rlc_init(struct amdgpu_device *adev)
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
return 0;
}
@ -5569,7 +5569,8 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
return 0;
}
static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
struct amdgpu_ring *ring, unsigned vmid)
{
u32 reg, pre_data, data;

3
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
View File

@ -762,7 +762,7 @@ static int gfx_v12_0_rlc_init(struct amdgpu_device *adev)
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
return 0;
}
@ -3957,6 +3957,7 @@ static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
}
static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
int xcc_id,
struct amdgpu_ring *ring,
unsigned vmid)
{

5
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View File

@ -3245,7 +3245,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
return 0;
}
@ -3471,7 +3471,8 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
return 0;
}
static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
struct amdgpu_ring *ring, unsigned vmid)
{
u32 data;

5
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View File

@ -1274,7 +1274,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
return 0;
}
@ -5541,7 +5541,8 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
}
}
static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
struct amdgpu_ring *ring, unsigned vmid)
{
u32 data;

3
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -5171,7 +5171,8 @@ static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,
WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
}
static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
struct amdgpu_ring *ring, unsigned int vmid)
{
amdgpu_gfx_off_ctrl(adev, false);

12
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
View File

@ -1455,7 +1455,7 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
{
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
return 0;
}
@ -1666,12 +1666,12 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
return 0;
}
static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring,
unsigned vmid)
static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,
int inst, struct amdgpu_ring *ring, unsigned int vmid)
{
u32 reg, pre_data, data;
reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL);
if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
pre_data = RREG32_NO_KIQ(reg);
else
@ -1682,9 +1682,9 @@ static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu
if (pre_data != data) {
if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data);
} else
WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data);
}
}