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riscv: dts: spacemit: PCIe and PHY-related updates
Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 board. The combo PHY is used for USB on this board, and that will be enabled when USB 3 support is accepted. The combo PHY must perform a calibration step to determine configuration values used by the PCIe-only PHYs. As a result, it must be enabled if either of the other two PHYs is enabled. Signed-off-by: Alex Elder <elder@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Tested-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251218151235.454997-6-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
This commit is contained in:
Alex Elder
Yixun Lan
parent
73a6c811fa
commit
0be016a4b5
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@ -61,6 +61,12 @@ reg_vcc_4v: vcc-4v {
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};
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};
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&combo_phy {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_3_cfg>;
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status = "okay";
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};
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&emmc {
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bus-width = <8>;
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mmc-hs400-1_8v;
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@ -272,6 +278,36 @@ dldo7 {
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};
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};
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&pcie1_phy {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_3_cfg>;
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status = "okay";
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};
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&pcie1_port {
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phys = <&pcie1_phy>;
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};
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&pcie1 {
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vpcie3v3-supply = <&pcie_vcc_3v3>;
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status = "okay";
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};
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&pcie2_phy {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2_4_cfg>;
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status = "okay";
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};
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&pcie2_port {
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phys = <&pcie2_phy>;
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};
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&pcie2 {
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vpcie3v3-supply = <&pcie_vcc_3v3>;
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status = "okay";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_2_cfg>;
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@ -530,6 +530,39 @@ uart9-2-pins {
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};
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};
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pcie0_3_cfg: pcie0-3-cfg {
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pcie0-3-pins {
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pinmux = <K1_PADCONF(54, 3)>, /* PERST# */
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<K1_PADCONF(55, 3)>, /* WAKE# */
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<K1_PADCONF(53, 3)>; /* CLKREQ# */
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bias-pull-up = <0>;
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drive-strength = <21>;
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};
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};
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pcie1_3_cfg: pcie1-3-cfg {
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pcie1-3-pins {
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pinmux = <K1_PADCONF(59, 4)>, /* PERST# */
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<K1_PADCONF(60, 4)>, /* WAKE# */
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<K1_PADCONF(61, 4)>; /* CLKREQ# */
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bias-pull-up = <0>;
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drive-strength = <21>;
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};
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};
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pcie2_4_cfg: pcie2-4-cfg {
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pcie2-4-pins {
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pinmux = <K1_PADCONF(62, 4)>, /* PERST# */
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<K1_PADCONF(112, 3)>, /* WAKE# */
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<K1_PADCONF(117, 4)>; /* CLKREQ# */
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bias-pull-up = <0>;
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drive-strength = <21>;
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};
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};
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pwm14_1_cfg: pwm14-1-cfg {
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pwm14-1-pins {
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pinmux = <K1_PADCONF(44, 4)>;
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@ -4,6 +4,7 @@
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*/
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#include <dt-bindings/clock/spacemit,k1-syscon.h>
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#include <dt-bindings/phy/phy.h>
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/dts-v1/;
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/ {
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@ -423,6 +424,52 @@ i2c5: i2c@d4013800 {
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status = "disabled";
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};
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combo_phy: phy@c0b10000 {
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compatible = "spacemit,k1-combo-phy";
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reg = <0x0 0xc0b10000 0x0 0x1000>;
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clocks = <&vctcxo_24m>,
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<&syscon_apmu CLK_PCIE0_DBI>,
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<&syscon_apmu CLK_PCIE0_MASTER>,
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<&syscon_apmu CLK_PCIE0_SLAVE>;
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clock-names = "refclk",
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"dbi",
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"mstr",
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"slv";
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resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
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<&syscon_apmu RESET_PCIE0_DBI>,
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<&syscon_apmu RESET_PCIE0_MASTER>,
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<&syscon_apmu RESET_PCIE0_SLAVE>;
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reset-names = "phy",
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"dbi",
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"mstr",
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"slv";
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#phy-cells = <1>;
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spacemit,apmu = <&syscon_apmu>;
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status = "disabled";
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};
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pcie1_phy: phy@c0c10000 {
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compatible = "spacemit,k1-pcie-phy";
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reg = <0x0 0xc0c10000 0x0 0x1000>;
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clocks = <&vctcxo_24m>;
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clock-names = "refclk";
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resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
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reset-names = "phy";
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#phy-cells = <0>;
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status = "disabled";
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};
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pcie2_phy: phy@c0d10000 {
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compatible = "spacemit,k1-pcie-phy";
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reg = <0x0 0xc0d10000 0x0 0x1000>;
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clocks = <&vctcxo_24m>;
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clock-names = "refclk";
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resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
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reset-names = "phy";
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#phy-cells = <0>;
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status = "disabled";
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};
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syscon_apbc: system-controller@d4015000 {
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compatible = "spacemit,k1-syscon-apbc";
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reg = <0x0 0xd4015000 0x0 0x1000>;
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@ -969,6 +1016,135 @@ pcie-bus {
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#size-cells = <2>;
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dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
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<0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
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pcie0: pcie@ca000000 {
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device_type = "pci";
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compatible = "spacemit,k1-pcie";
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reg = <0x0 0xca000000 0x0 0x00001000>,
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<0x0 0xca300000 0x0 0x0001ff24>,
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<0x0 0x8f000000 0x0 0x00002000>,
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<0x0 0xc0b20000 0x0 0x00001000>;
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reg-names = "dbi",
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"atu",
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"config",
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"link";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>,
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<0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>;
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interrupts = <141>;
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interrupt-names = "msi";
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clocks = <&syscon_apmu CLK_PCIE0_DBI>,
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<&syscon_apmu CLK_PCIE0_MASTER>,
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<&syscon_apmu CLK_PCIE0_SLAVE>;
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clock-names = "dbi",
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"mstr",
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"slv";
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resets = <&syscon_apmu RESET_PCIE0_DBI>,
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<&syscon_apmu RESET_PCIE0_MASTER>,
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<&syscon_apmu RESET_PCIE0_SLAVE>;
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reset-names = "dbi",
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"mstr",
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"slv";
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spacemit,apmu = <&syscon_apmu 0x03cc>;
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status = "disabled";
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pcie0_port: pcie@0 {
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device_type = "pci";
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compatible = "pciclass,0604";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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pcie1: pcie@ca400000 {
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device_type = "pci";
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compatible = "spacemit,k1-pcie";
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reg = <0x0 0xca400000 0x0 0x00001000>,
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<0x0 0xca700000 0x0 0x0001ff24>,
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<0x0 0x9f000000 0x0 0x00002000>,
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<0x0 0xc0c20000 0x0 0x00001000>;
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reg-names = "dbi",
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"atu",
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"config",
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"link";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>,
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<0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>;
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interrupts = <142>;
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interrupt-names = "msi";
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clocks = <&syscon_apmu CLK_PCIE1_DBI>,
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<&syscon_apmu CLK_PCIE1_MASTER>,
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<&syscon_apmu CLK_PCIE1_SLAVE>;
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clock-names = "dbi",
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"mstr",
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"slv";
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resets = <&syscon_apmu RESET_PCIE1_DBI>,
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<&syscon_apmu RESET_PCIE1_MASTER>,
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<&syscon_apmu RESET_PCIE1_SLAVE>;
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reset-names = "dbi",
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"mstr",
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"slv";
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spacemit,apmu = <&syscon_apmu 0x3d4>;
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status = "disabled";
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pcie1_port: pcie@0 {
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device_type = "pci";
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compatible = "pciclass,0604";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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pcie2: pcie@ca800000 {
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device_type = "pci";
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compatible = "spacemit,k1-pcie";
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reg = <0x0 0xca800000 0x0 0x00001000>,
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<0x0 0xcab00000 0x0 0x0001ff24>,
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<0x0 0xb7000000 0x0 0x00002000>,
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<0x0 0xc0d20000 0x0 0x00001000>;
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reg-names = "dbi",
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"atu",
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"config",
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"link";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>,
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<0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>,
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<0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>;
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interrupts = <143>;
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interrupt-names = "msi";
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clocks = <&syscon_apmu CLK_PCIE2_DBI>,
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<&syscon_apmu CLK_PCIE2_MASTER>,
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<&syscon_apmu CLK_PCIE2_SLAVE>;
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clock-names = "dbi",
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"mstr",
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"slv";
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resets = <&syscon_apmu RESET_PCIE2_DBI>,
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<&syscon_apmu RESET_PCIE2_MASTER>,
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<&syscon_apmu RESET_PCIE2_SLAVE>;
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reset-names = "dbi",
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"mstr",
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"slv";
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spacemit,apmu = <&syscon_apmu 0x3dc>;
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status = "disabled";
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pcie2_port: pcie@0 {
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device_type = "pci";
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compatible = "pciclass,0604";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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};
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storage-bus {
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