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net/mlx5: Drop redundant esw_cap, reuse e_switch_cap

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esw_manager_vport_number{,_valid} and merged_eswitch were read through a
separate mlx5_ifc_esw_cap_bits struct, but these bits live in the
e-switch capability that mlx5_ifc_e_switch_cap_bits already describes
(both overlay the same QUERY_HCA_CAP op_mod 0x9 output).

Add esw_manager_vport_number{,_valid} to mlx5_ifc_e_switch_cap_bits at
the same offsets, drop the redundant mlx5_ifc_esw_cap_bits and its
hca_cap_union member, and switch the only user (hws/cmd.c) to
capability.e_switch_cap.

Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20260713084320.1015240-2-tariqt@nvidia.com
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
This commit is contained in:
Shay Drory 2026-07-13 11:43:19 +03:00 committed by Leon Romanovsky
parent a13c140cc2
commit 0b7b175023
2 changed files with 8 additions and 19 deletions
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6
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c
View File

@ -1172,13 +1172,13 @@ int mlx5hws_cmd_query_caps(struct mlx5_core_dev *mdev,
}
if (MLX5_GET(query_hca_cap_out, out,
capability.esw_cap.esw_manager_vport_number_valid))
capability.e_switch_cap.esw_manager_vport_number_valid))
caps->eswitch_manager_vport_number =
MLX5_GET(query_hca_cap_out, out,
capability.esw_cap.esw_manager_vport_number);
capability.e_switch_cap.esw_manager_vport_number);
caps->merged_eswitch = MLX5_GET(query_hca_cap_out, out,
capability.esw_cap.merged_eswitch);
capability.e_switch_cap.merged_eswitch);
}
ret = mlx5_cmd_exec(mdev, in, sizeof(in), out, out_size);

21
include/linux/mlx5/mlx5_ifc.h
View File

@ -1042,20 +1042,6 @@ struct mlx5_ifc_wqe_based_flow_table_cap_bits {
u8 reserved_at_1c1[0x1f];
};
struct mlx5_ifc_esw_cap_bits {
u8 reserved_at_0[0x1d];
u8 merged_eswitch[0x1];
u8 reserved_at_1e[0x2];
u8 reserved_at_20[0x40];
u8 esw_manager_vport_number_valid[0x1];
u8 reserved_at_61[0xf];
u8 esw_manager_vport_number[0x10];
u8 reserved_at_80[0x780];
};
enum {
MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
MLX5_COUNTER_FLOW_ESWITCH = 0x1,
@ -1096,7 +1082,11 @@ struct mlx5_ifc_e_switch_cap_bits {
u8 log_max_esw_sf[0x5];
u8 esw_sf_base_id[0x10];
u8 reserved_at_60[0x7a0];
u8 esw_manager_vport_number_valid[0x1];
u8 reserved_at_61[0xf];
u8 esw_manager_vport_number[0x10];
u8 reserved_at_80[0x780];
};
@ -3859,7 +3849,6 @@ union mlx5_ifc_hca_cap_union_bits {
struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
struct mlx5_ifc_esw_cap_bits esw_cap;
struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
struct mlx5_ifc_qos_cap_bits qos_cap;