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This pull request contains Broadcom ARM-based SoCs Device Tree changes

Browse Source 
for 6.4, please pull the following:
 
 - William adds the new-style High Speed SPI controller node to the BCA
   SoCs
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmQ0mX8ACgkQh9CWnEQH
 BwQhjhAAyHMwI6uMjnEHf150ggtuckE2Lijz74c0O1RmcINL+fQiiEVWLjO2ongv
 n+hNfndWynGjxBpkj2JSwUaSKTuxJMGqb6k5ky1O8+DQUpagKArXMRXkwU4V/ZAk
 KU2JtQ0MA0ACzBKJh4uIftKsYwZ84tdHjNX+gUvex8qp0TBNNj+3bvPs/zcoY7NB
 BHpigD7NAPlnKcUEzSlIYcief+az2KMl/d5+UKIE8nXh+DPju1PHsxLxQK9UOuSN
 kmJ9l/yjSHu5eyZFtUIkkT5DybBtWs73T9lN7QPp2AP/caxsJFInlBaHTQKRGdQa
 9Sln6cGxPMvwHYFDLXplX8vNprad5g1ErR0dJhb/6PhAUY7DnnhEysPs+odhSKgD
 BUHIkwDTR7xGhTe/7SfCFvxF2xXCAgS+cakCPv+s0+1DAR4MQW4DIsKHLsmEmOlI
 AeIA67TGxBmfihH1lioUC2YVaEtSntScJ+Kf6WRF/bcCcylSAKYAa3PdCZ9ZOAbL
 enJXV0X0+UihSTPMzdBFncHfRR7hNaCR7PP7pBb65i8mvI9WSERHGmdC+/FkQDMY
 X/CJBH28vm+aAFkei2ZxXjb6ZGRE+n/8oTUP+pqs1S93k3IET8a7DG7BGIEYIcy3
 6UCYj1rvc7WhSTxzRxqhevDVzIQCm/X2x6qzcWVbgRdDQnRrCEs=
 =H9IN
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmQ5eAIACgkQYKtH/8kJ
 UifB9hAAiTgIFHleb4uzY4ahUVMl9vhMlpDepRqh57T+WjCyKFTu0ybMzV6BWMTQ
 glMlBm1xAO7h9L9WMnoIrCLqjuyCifob6Q9/126KuKhbwqzpVxUStvxnhOzHlv1K
 54K+LS5gl2CKNkpdBQFGCdPsWvL2ICCc6DUS1DUuY+8zZKwGG73JLqeodAt1Juhr
 UCWb2qewAWRi16h9L9ZGTrsOF90k3hDAenT77YGLnCBwOn0N3umO+lGXtqd+PJ4B
 FkLnv0sEC4bsJbp9rxfg7zGZdgdFznT0257SmloYmhWCdWa5+DuKIOZ6Lblh9QCi
 22M+iM9vM2K99XfDo0Kr9GDL9Dcf2e4Ly2on3RZUVT5o+C7bmt4C9JGCCxlR5SJG
 Swne3l2tfExHkPS3SZyKjHKuv68Mj055HBldBVedktX0ZmalFnT0HitVqTflx4+j
 HWbRaPL0YXd7lN2rdfudbUtwGrrLjvPr/UhDGHfRR9jsHX6b0UdVQbdRatfzdAiO
 sWo0bGlbNZYP8IPK3/OlQyhJdVZlXKUIx6ZGISWYyLR0jrRDbnYVhs1a72SJfC/e
 Hxn3iQOI/vDw5+wcOz0oYhojKHgN/SSR9WwES9tSpyp6aKbRzKSGiADihAIx3psU
 aKVgZeLYZGzABza6zgoE/0U2Sa8mChDkkzF2FnFLUtXz4Q/eZFs=
 =HvvQ
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-6.4/devicetree' of https://github.com/Broadcom/stblinux into soc/dt

This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 6.4, please pull the following:

- William adds the new-style High Speed SPI controller node to the BCA
  SoCs

* tag 'arm-soc/for-6.4/devicetree' of https://github.com/Broadcom/stblinux:
  ARM: dts: broadcom: bcmbca: Add spi controller node

Link: https://lore.kernel.org/r/20230410232606.1917803-1-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-04-14 17:57:53 +02:00
commit 0b3751dc8d
17 changed files with 184 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/arm/boot/dts/bcm47622.dtsi
View File

@ -88,6 +88,12 @@ uart_clk: uart-clk {
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
};
psci {
@ -119,6 +125,18 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0";
reg = <0x1000 0x600>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsspi_pll &hsspi_pll>;
clock-names = "hsspi", "pll";
num-cs = <8>;
status = "disabled";
};
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;

18
arch/arm/boot/dts/bcm63138.dtsi
View File

@ -66,6 +66,12 @@ apb_clk: apb_clk {
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
};
};
/* ARM bus */
@ -203,6 +209,18 @@ serial1: serial@620 {
status = "disabled";
};
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0";
reg = <0x1000 0x600>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsspi_pll &hsspi_pll>;
clock-names = "hsspi", "pll";
num-cs = <8>;
status = "disabled";
};
nand_controller: nand-controller@2000 {
#address-cells = <1>;
#size-cells = <0>;

18
arch/arm/boot/dts/bcm63148.dtsi
View File

@ -60,6 +60,12 @@ periph_clk: periph-clk {
#clock-cells = <0>;
clock-frequency = <50000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
};
};
psci {
@ -100,5 +106,17 @@ uart0: serial@600 {
clock-names = "refclk";
status = "disabled";
};
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0";
reg = <0x1000 0x600>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsspi_pll &hsspi_pll>;
clock-names = "hsspi", "pll";
num-cs = <8>;
status = "disabled";
};
};
};

19
arch/arm/boot/dts/bcm63178.dtsi
View File

@ -71,6 +71,7 @@ periph_clk: periph-clk {
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
@ -78,6 +79,12 @@ uart_clk: uart-clk {
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
};
psci {
@ -109,6 +116,18 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0";
reg = <0x1000 0x600>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsspi_pll &hsspi_pll>;
clock-names = "hsspi", "pll";
num-cs = <8>;
status = "disabled";
};
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;

19
arch/arm/boot/dts/bcm6756.dtsi
View File

@ -88,6 +88,12 @@ uart_clk: uart-clk {
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
};
psci {
@ -119,6 +125,19 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
reg = <0x1000 0x600>, <0x2610 0x4>;
reg-names = "hsspi", "spim-ctrl";
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsspi_pll &hsspi_pll>;
clock-names = "hsspi", "pll";
num-cs = <8>;
status = "disabled";
};
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;

18
arch/arm/boot/dts/bcm6846.dtsi
View File

@ -61,6 +61,12 @@ periph_clk: periph-clk {
#clock-cells = <0>;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
};
};
psci {
@ -100,5 +106,17 @@ uart0: serial@640 {
clock-names = "refclk";
status = "disabled";
};
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0";
reg = <0x1000 0x600>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsspi_pll &hsspi_pll>;
clock-names = "hsspi", "pll";
num-cs = <8>;
status = "disabled";
};
};
};

19
arch/arm/boot/dts/bcm6855.dtsi
View File

@ -78,6 +78,12 @@ uart_clk: uart-clk {
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
};
psci {
@ -109,6 +115,19 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1";
reg = <0x1000 0x600>, <0x2610 0x4>;
reg-names = "hsspi", "spim-ctrl";
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsspi_pll &hsspi_pll>;
clock-names = "hsspi", "pll";
num-cs = <8>;
status = "disabled";
};
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;

19
arch/arm/boot/dts/bcm6878.dtsi
View File

@ -61,6 +61,7 @@ periph_clk: periph-clk {
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
@ -68,6 +69,12 @@ uart_clk: uart-clk {
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
};
psci {
@ -100,6 +107,18 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0";
reg = <0x1000 0x600>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsspi_pll &hsspi_pll>;
clock-names = "hsspi", "pll";
num-cs = <8>;
status = "disabled";
};
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;

4
arch/arm/boot/dts/bcm947622.dts
View File

@ -28,3 +28,7 @@ memory@0 {
&uart0 {
status = "okay";
};
&hsspi {
status = "okay";
};

4
arch/arm/boot/dts/bcm963138.dts
View File

@ -25,3 +25,7 @@ memory@0 {
&serial0 {
status = "okay";
};
&hsspi {
status = "okay";
};

4
arch/arm/boot/dts/bcm963138dvt.dts
View File

@ -50,3 +50,7 @@ &ahci {
&sata_phy {
status = "okay";
};
&hsspi {
status = "okay";
};

4
arch/arm/boot/dts/bcm963148.dts
View File

@ -28,3 +28,7 @@ memory@0 {
&uart0 {
status = "okay";
};
&hsspi {
status = "okay";
};

4
arch/arm/boot/dts/bcm963178.dts
View File

@ -28,3 +28,7 @@ memory@0 {
&uart0 {
status = "okay";
};
&hsspi {
status = "okay";
};

4
arch/arm/boot/dts/bcm96756.dts
View File

@ -28,3 +28,7 @@ memory@0 {
&uart0 {
status = "okay";
};
&hsspi {
status = "okay";
};

4
arch/arm/boot/dts/bcm96846.dts
View File

@ -28,3 +28,7 @@ memory@0 {
&uart0 {
status = "okay";
};
&hsspi {
status = "okay";
};

4
arch/arm/boot/dts/bcm96855.dts
View File

@ -28,3 +28,7 @@ memory@0 {
&uart0 {
status = "okay";
};
&hsspi {
status = "okay";
};

4
arch/arm/boot/dts/bcm96878.dts
View File

@ -28,3 +28,7 @@ memory@0 {
&uart0 {
status = "okay";
};
&hsspi {
status = "okay";
};