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ASoC: rk3308_codec: clean up unnecessary AGC controls

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The AGC may bring non-linear ADC processing, that makes it
difficult for back-end audio algorithms to use NLP, so we
usually turn them off.
In addition, it seems too many controls and easy to confuse,
let's remove them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: If17387b0db055942acf1d7e9a5b8b6b9057f1c78
This commit is contained in:
Xing Zheng 2021-09-11 16:54:48 +08:00 committed by Tao Huang
parent dc43d8633b
commit 0b095228a2
1 changed files with 1 additions and 419 deletions
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420
sound/soc/codecs/rk3308_codec.c
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@ -194,14 +194,6 @@ struct rk3308_codec_priv {
int ext_micbias;
int pm_state;
/* AGC L/R Off/on */
unsigned int agc_l[ADC_LR_GROUP_MAX];
unsigned int agc_r[ADC_LR_GROUP_MAX];
/* AGC L/R Approximate Sample Rate */
unsigned int agc_asr_l[ADC_LR_GROUP_MAX];
unsigned int agc_asr_r[ADC_LR_GROUP_MAX];
/* ADC MIC Mute/Work */
unsigned int mic_mute_l[ADC_LR_GROUP_MAX];
unsigned int mic_mute_r[ADC_LR_GROUP_MAX];
@ -232,12 +224,6 @@ struct rk3308_codec_priv {
#endif
};
static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_gain_tlv,
-1800, 150, 2850);
static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_max_gain_tlv,
-1350, 600, 2850);
static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_min_gain_tlv,
-1800, 600, 2400);
static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_alc_gain_tlv,
-1800, 150, 2850);
static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_lineout_gain_tlv,
@ -281,14 +267,6 @@ static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol,
@ -355,18 +333,6 @@ static const struct soc_enum rk3308_hpf_enum_array[] = {
SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(offon_text), offon_text),
};
/* ALC AGC Switch */
static const struct soc_enum rk3308_agc_enum_array[] = {
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text),
SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(offon_text), offon_text),
SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(offon_text), offon_text),
SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(offon_text), offon_text),
SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(offon_text), offon_text),
SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(offon_text), offon_text),
SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(offon_text), offon_text),
SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(offon_text), offon_text),
};
/* ADC MIC Mute/Work Switch */
static const struct soc_enum rk3308_mic_mute_enum_array[] = {
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(mute_text), mute_text),
@ -379,40 +345,6 @@ static const struct soc_enum rk3308_mic_mute_enum_array[] = {
SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(mute_text), mute_text),
};
/* ALC AGC Approximate Sample Rate */
#define AGC_ASR_NUM 8
#define AGC_ASR_96KHZ 0
#define AGC_ASR_48KHZ 1
#define AGC_ASR_44_1KHZ 2
#define AGC_ASR_32KHZ 3
#define AGC_ASR_24KHZ 4
#define AGC_ASR_16KHZ 5
#define AGC_ASR_12KHZ 6
#define AGC_ASR_8KHZ 7
static const char *agc_asr_text[AGC_ASR_NUM] = {
[AGC_ASR_96KHZ] = "96KHz",
[AGC_ASR_48KHZ] = "48KHz",
[AGC_ASR_44_1KHZ] = "44.1KHz",
[AGC_ASR_32KHZ] = "32KHz",
[AGC_ASR_24KHZ] = "24KHz",
[AGC_ASR_16KHZ] = "16KHz",
[AGC_ASR_12KHZ] = "12KHz",
[AGC_ASR_8KHZ] = "8KHz",
};
static const struct soc_enum rk3308_agc_asr_enum_array[] = {
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text),
SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text),
SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text),
SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text),
SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text),
SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text),
SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text),
SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text),
};
static const struct snd_kcontrol_new mic_gains_a[] = {
/* ADC MIC */
SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Left Gain",
@ -550,201 +482,6 @@ static const struct snd_kcontrol_new mic_gains_b[] = {
};
static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = {
/* ALC AGC Group */
SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Volume",
RK3308_ALC_L_DIG_CON03(0),
RK3308_AGC_PGA_GAIN_SFT,
RK3308_AGC_PGA_GAIN_MIN,
RK3308_AGC_PGA_GAIN_MAX,
0, rk3308_codec_alc_agc_grp_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Volume",
RK3308_ALC_R_DIG_CON03(0),
RK3308_AGC_PGA_GAIN_SFT,
RK3308_AGC_PGA_GAIN_MIN,
RK3308_AGC_PGA_GAIN_MAX,
0, rk3308_codec_alc_agc_grp_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Volume",
RK3308_ALC_L_DIG_CON03(1),
RK3308_AGC_PGA_GAIN_SFT,
RK3308_AGC_PGA_GAIN_MIN,
RK3308_AGC_PGA_GAIN_MAX,
0, rk3308_codec_alc_agc_grp_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Volume",
RK3308_ALC_R_DIG_CON03(1),
RK3308_AGC_PGA_GAIN_SFT,
RK3308_AGC_PGA_GAIN_MIN,
RK3308_AGC_PGA_GAIN_MAX,
0, rk3308_codec_alc_agc_grp_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Volume",
RK3308_ALC_L_DIG_CON03(2),
RK3308_AGC_PGA_GAIN_SFT,
RK3308_AGC_PGA_GAIN_MIN,
RK3308_AGC_PGA_GAIN_MAX,
0, rk3308_codec_alc_agc_grp_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Volume",
RK3308_ALC_R_DIG_CON03(2),
RK3308_AGC_PGA_GAIN_SFT,
RK3308_AGC_PGA_GAIN_MIN,
RK3308_AGC_PGA_GAIN_MAX,
0, rk3308_codec_alc_agc_grp_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Volume",
RK3308_ALC_L_DIG_CON03(3),
RK3308_AGC_PGA_GAIN_SFT,
RK3308_AGC_PGA_GAIN_MIN,
RK3308_AGC_PGA_GAIN_MAX,
0, rk3308_codec_alc_agc_grp_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Volume",
RK3308_ALC_R_DIG_CON03(3),
RK3308_AGC_PGA_GAIN_SFT,
RK3308_AGC_PGA_GAIN_MIN,
RK3308_AGC_PGA_GAIN_MAX,
0, rk3308_codec_alc_agc_grp_gain_tlv),
/* ALC AGC MAX */
SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Max Volume",
RK3308_ALC_L_DIG_CON09(0),
RK3308_AGC_MAX_GAIN_PGA_SFT,
RK3308_AGC_MAX_GAIN_PGA_MIN,
RK3308_AGC_MAX_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_max_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Max Volume",
RK3308_ALC_R_DIG_CON09(0),
RK3308_AGC_MAX_GAIN_PGA_SFT,
RK3308_AGC_MAX_GAIN_PGA_MIN,
RK3308_AGC_MAX_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_max_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Max Volume",
RK3308_ALC_L_DIG_CON09(1),
RK3308_AGC_MAX_GAIN_PGA_SFT,
RK3308_AGC_MAX_GAIN_PGA_MIN,
RK3308_AGC_MAX_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_max_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Max Volume",
RK3308_ALC_R_DIG_CON09(1),
RK3308_AGC_MAX_GAIN_PGA_SFT,
RK3308_AGC_MAX_GAIN_PGA_MIN,
RK3308_AGC_MAX_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_max_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Max Volume",
RK3308_ALC_L_DIG_CON09(2),
RK3308_AGC_MAX_GAIN_PGA_SFT,
RK3308_AGC_MAX_GAIN_PGA_MIN,
RK3308_AGC_MAX_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_max_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Max Volume",
RK3308_ALC_R_DIG_CON09(2),
RK3308_AGC_MAX_GAIN_PGA_SFT,
RK3308_AGC_MAX_GAIN_PGA_MIN,
RK3308_AGC_MAX_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_max_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Max Volume",
RK3308_ALC_L_DIG_CON09(3),
RK3308_AGC_MAX_GAIN_PGA_SFT,
RK3308_AGC_MAX_GAIN_PGA_MIN,
RK3308_AGC_MAX_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_max_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Max Volume",
RK3308_ALC_R_DIG_CON09(3),
RK3308_AGC_MAX_GAIN_PGA_SFT,
RK3308_AGC_MAX_GAIN_PGA_MIN,
RK3308_AGC_MAX_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_max_gain_tlv),
/* ALC AGC MIN */
SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Min Volume",
RK3308_ALC_L_DIG_CON09(0),
RK3308_AGC_MIN_GAIN_PGA_SFT,
RK3308_AGC_MIN_GAIN_PGA_MIN,
RK3308_AGC_MIN_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_min_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Min Volume",
RK3308_ALC_R_DIG_CON09(0),
RK3308_AGC_MIN_GAIN_PGA_SFT,
RK3308_AGC_MIN_GAIN_PGA_MIN,
RK3308_AGC_MIN_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_min_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Min Volume",
RK3308_ALC_L_DIG_CON09(1),
RK3308_AGC_MIN_GAIN_PGA_SFT,
RK3308_AGC_MIN_GAIN_PGA_MIN,
RK3308_AGC_MIN_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_min_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Min Volume",
RK3308_ALC_R_DIG_CON09(1),
RK3308_AGC_MIN_GAIN_PGA_SFT,
RK3308_AGC_MIN_GAIN_PGA_MIN,
RK3308_AGC_MIN_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_min_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Min Volume",
RK3308_ALC_L_DIG_CON09(2),
RK3308_AGC_MIN_GAIN_PGA_SFT,
RK3308_AGC_MIN_GAIN_PGA_MIN,
RK3308_AGC_MIN_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_min_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Min Volume",
RK3308_ALC_R_DIG_CON09(2),
RK3308_AGC_MIN_GAIN_PGA_SFT,
RK3308_AGC_MIN_GAIN_PGA_MIN,
RK3308_AGC_MIN_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_min_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Min Volume",
RK3308_ALC_L_DIG_CON09(3),
RK3308_AGC_MIN_GAIN_PGA_SFT,
RK3308_AGC_MIN_GAIN_PGA_MIN,
RK3308_AGC_MIN_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_min_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Min Volume",
RK3308_ALC_R_DIG_CON09(3),
RK3308_AGC_MIN_GAIN_PGA_SFT,
RK3308_AGC_MIN_GAIN_PGA_MIN,
RK3308_AGC_MIN_GAIN_PGA_MAX,
0, rk3308_codec_alc_agc_grp_min_gain_tlv),
/* ALC AGC Switch */
SOC_ENUM_EXT("ALC AGC Group 0 Left Switch", rk3308_agc_enum_array[0],
rk3308_codec_agc_get, rk3308_codec_agc_put),
SOC_ENUM_EXT("ALC AGC Group 0 Right Switch", rk3308_agc_enum_array[1],
rk3308_codec_agc_get, rk3308_codec_agc_put),
SOC_ENUM_EXT("ALC AGC Group 1 Left Switch", rk3308_agc_enum_array[2],
rk3308_codec_agc_get, rk3308_codec_agc_put),
SOC_ENUM_EXT("ALC AGC Group 1 Right Switch", rk3308_agc_enum_array[3],
rk3308_codec_agc_get, rk3308_codec_agc_put),
SOC_ENUM_EXT("ALC AGC Group 2 Left Switch", rk3308_agc_enum_array[4],
rk3308_codec_agc_get, rk3308_codec_agc_put),
SOC_ENUM_EXT("ALC AGC Group 2 Right Switch", rk3308_agc_enum_array[5],
rk3308_codec_agc_get, rk3308_codec_agc_put),
SOC_ENUM_EXT("ALC AGC Group 3 Left Switch", rk3308_agc_enum_array[6],
rk3308_codec_agc_get, rk3308_codec_agc_put),
SOC_ENUM_EXT("ALC AGC Group 3 Right Switch", rk3308_agc_enum_array[7],
rk3308_codec_agc_get, rk3308_codec_agc_put),
/* ALC AGC Approximate Sample Rate */
SOC_ENUM_EXT("AGC Group 0 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[0],
rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
SOC_ENUM_EXT("AGC Group 0 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[1],
rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
SOC_ENUM_EXT("AGC Group 1 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[2],
rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
SOC_ENUM_EXT("AGC Group 1 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[3],
rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
SOC_ENUM_EXT("AGC Group 2 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[4],
rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
SOC_ENUM_EXT("AGC Group 2 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[5],
rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
SOC_ENUM_EXT("AGC Group 3 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[6],
rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
SOC_ENUM_EXT("AGC Group 3 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[7],
rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put),
/* ADC MICBIAS Voltage */
SOC_ENUM_EXT("ADC MICBIAS Voltage", rk3308_micbias_volts_enum_array[0],
rk3308_codec_micbias_volts_get, rk3308_codec_micbias_volts_put),
@ -882,156 +619,6 @@ static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = {
0, rk3308_codec_dac_hpmix_gain_tlv),
};
static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
dev_err(rk3308->plat_dev,
"%s: Invalid ADC grp: %d\n", __func__, e->reg);
return -EINVAL;
}
if (e->shift_l)
ucontrol->value.integer.value[0] = rk3308->agc_r[e->reg];
else
ucontrol->value.integer.value[0] = rk3308->agc_l[e->reg];
return 0;
}
static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int value = ucontrol->value.integer.value[0];
int grp = e->reg;
if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
dev_err(rk3308->plat_dev,
"%s: Invalid ADC grp: %d\n", __func__, e->reg);
return -EINVAL;
}
if (value) {
/* ALC AGC On */
if (e->shift_l) {
/* ALC AGC Right On */
regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp),
RK3308_AGC_FUNC_SEL_MSK,
RK3308_AGC_FUNC_SEL_EN);
regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp),
RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK,
RK3308_ADC_ALCR_CON_GAIN_PGAR_EN);
rk3308->agc_r[e->reg] = 1;
} else {
/* ALC AGC Left On */
regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp),
RK3308_AGC_FUNC_SEL_MSK,
RK3308_AGC_FUNC_SEL_EN);
regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp),
RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK,
RK3308_ADC_ALCL_CON_GAIN_PGAL_EN);
rk3308->agc_l[e->reg] = 1;
}
} else {
/* ALC AGC Off */
if (e->shift_l) {
/* ALC AGC Right Off */
regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp),
RK3308_AGC_FUNC_SEL_MSK,
RK3308_AGC_FUNC_SEL_DIS);
regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp),
RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK,
RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS);
rk3308->agc_r[e->reg] = 0;
} else {
/* ALC AGC Left Off */
regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp),
RK3308_AGC_FUNC_SEL_MSK,
RK3308_AGC_FUNC_SEL_DIS);
regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp),
RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK,
RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS);
rk3308->agc_l[e->reg] = 0;
}
}
return 0;
}
static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int value;
int grp = e->reg;
if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
dev_err(rk3308->plat_dev,
"%s: Invalid ADC grp: %d\n", __func__, e->reg);
return -EINVAL;
}
if (e->shift_l) {
regmap_read(rk3308->regmap, RK3308_ALC_R_DIG_CON04(grp), &value);
rk3308->agc_asr_r[e->reg] = value >> RK3308_AGC_APPROX_RATE_SFT;
ucontrol->value.integer.value[0] = rk3308->agc_asr_r[e->reg];
} else {
regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON04(grp), &value);
rk3308->agc_asr_l[e->reg] = value >> RK3308_AGC_APPROX_RATE_SFT;
ucontrol->value.integer.value[0] = rk3308->agc_asr_l[e->reg];
}
return 0;
}
static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int value;
int grp = e->reg;
if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) {
dev_err(rk3308->plat_dev,
"%s: Invalid ADC grp: %d\n", __func__, e->reg);
return -EINVAL;
}
value = ucontrol->value.integer.value[0] << RK3308_AGC_APPROX_RATE_SFT;
if (e->shift_l) {
/* ALC AGC Right Approximate Sample Rate */
regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON04(grp),
RK3308_AGC_APPROX_RATE_MSK,
value);
rk3308->agc_asr_r[e->reg] = ucontrol->value.integer.value[0];
} else {
/* ALC AGC Left Approximate Sample Rate */
regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON04(grp),
RK3308_AGC_APPROX_RATE_MSK,
value);
rk3308->agc_asr_l[e->reg] = ucontrol->value.integer.value[0];
}
return 0;
}
static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@ -4074,13 +3661,8 @@ static int rk3308_codec_dapm_controls_prepare(struct rk3308_codec_priv *rk3308)
{
int grp;
for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) {
for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++)
rk3308->hpf_cutoff[grp] = 0;
rk3308->agc_l[grp] = 0;
rk3308->agc_r[grp] = 0;
rk3308->agc_asr_l[grp] = AGC_ASR_96KHZ;
rk3308->agc_asr_r[grp] = AGC_ASR_96KHZ;
}
rk3308_codec_dapm_mic_gains(rk3308);