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Merge branch 'net-fix-typos-and-repeated-words-in-comments'
Hemanth Selam says: ==================== net: fix typos and repeated words in comments Fix misspellings and repeated words in comments across the networking code, found with scripts/checkpatch.pl using the misspelling list in scripts/spelling.txt. Comments only, no code changes. ==================== Link: https://patch.msgid.link/20260908052602.27497-1-hemanth.selam@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
0abe877749
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@ -659,7 +659,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
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/* INT-triggle/SMB Control Register */
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#define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */
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#define SMB_STAT_TIMER_MASK 0xFFFFFF
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#define REG_TINT_TPD_THRESH 0x15C8 /* tpd th to trig intrrupt */
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#define REG_TINT_TPD_THRESH 0x15C8 /* tpd th to trig interrupt */
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/* Mail box */
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#define MB_RFDX_PROD_IDX_MASK 0xFFFF
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@ -381,7 +381,7 @@ struct atl1e_rx_page {
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u8 *addr; /* receive rage virtual address */
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dma_addr_t write_offset_dma; /* the DMA address which contain the
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receive data offset in the page */
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u32 *write_offset_addr; /* the virtaul address which contain
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u32 *write_offset_addr; /* the virtual address which contain
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the receive data offset in the page */
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u32 read_offset; /* the offset where we have read */
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};
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@ -369,7 +369,7 @@ static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
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*
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* hw - Struct containing variables accessed by shared code
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*
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* Sets bit 15 and 12 of the MII control regiser (for F001 bug)
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* Sets bit 15 and 12 of the MII control register (for F001 bug)
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*/
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int atl1e_phy_commit(struct atl1e_hw *hw)
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{
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@ -2117,7 +2117,7 @@ static int atl1e_suspend(struct pci_dev *pdev, pm_message_t state)
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wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
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if (wufc & AT_WUFC_LNKC) {
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/* if orignal link status is link, just wait for retrive link */
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/* if original link status is link, just wait for retrieve link */
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if (mii_bmsr_data & BMSR_LSTATUS) {
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for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
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msleep(100);
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@ -628,7 +628,7 @@ static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
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* Resets the PHY and make all config validate
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* hw - Struct containing variables accessed by shared code
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*
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* Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
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* Sets bit 15 and 12 of the MII Control register (for F001 bug)
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*/
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static s32 atl1_phy_reset(struct atl1_hw *hw)
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{
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@ -2591,7 +2591,7 @@ static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
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*
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* hw - Struct containing variables accessed by shared code
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*
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* Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
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* Sets bit 15 and 12 of the MII Control register (for F001 bug)
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*/
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static s32 atl2_phy_commit(struct atl2_hw *hw)
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{
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@ -1564,7 +1564,7 @@ static int bcm_enet_set_pauseparam(struct net_device *dev,
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if (priv->has_phy) {
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if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
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/* asymetric pause mode not supported,
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/* asymmetric pause mode not supported,
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* actually possible but integrated PHY has RO
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* asym_pause bit */
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return -EINVAL;
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@ -265,7 +265,7 @@ struct bcm_enet_priv {
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/* number of available descriptor for tx */
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int tx_desc_count;
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/* next tx descriptor avaiable */
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/* next tx descriptor available */
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int tx_curr_desc;
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/* next dirty tx descriptor to reclaim */
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@ -402,7 +402,7 @@ struct bcm_rsb {
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#define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \
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((i) * TDMA_DESC_RING_SIZE))
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/* Ring indexed register addreses */
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/* Ring indexed register addresses */
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#define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \
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RING_HEAD_TAIL_PTR)
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#define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \
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@ -280,7 +280,7 @@ enum {
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* (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
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* We must avoid coming up with cid 8 for iscsi since according to this method
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* the designated UIO cid will come out 0 and it has a special handling for that
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* case which doesn't suit us. Therefore will will cieling to closes cid which
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* case which doesn't suit us. Therefore will cieling to closes cid which
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* has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
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*/
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@ -666,7 +666,7 @@ struct bnx2x_fastpath {
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MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
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/* max BDs per tx packet w/o next_pages:
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* START_BD - describes packed
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* START_BD(splitted) - includes unpaged data segment for GSO
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* START_BD(split) - includes unpaged data segment for GSO
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* PARSING_BD - for TSO and CSUM data
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* PARSING_BD2 - for encapsulation data
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* Frag BDs - describes pages for frags
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@ -1986,7 +1986,7 @@ static void bnx2x_dcbnl_set_pg_tccfg_tx(struct net_device *netdev, int prio,
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return;
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/**
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* bw_pct ignored - band-width percentage devision between user
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* bw_pct ignored - band-width percentage division between user
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* priorities within the same group is not
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* standard and hence not supported
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*
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@ -2038,7 +2038,7 @@ static void bnx2x_dcbnl_get_pg_tccfg_tx(struct net_device *netdev, int prio,
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DP(BNX2X_MSG_DCB, "prio = %d\n", prio);
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/**
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* bw_pct ignored - band-width percentage devision between user
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* bw_pct ignored - band-width percentage division between user
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* priorities within the same group is not
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* standard and hence not supported
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*
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@ -2342,7 +2342,7 @@ struct shmem2_region {
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u32 oem_i2c_data_addr;
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};
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/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
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/* 9 entries for the C2S PCP map for each inner VLAN PCP + 1 default */
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/* For PCP values 0-3 use the map lower */
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/* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
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* 0x0000FF00 - PCP 2, 0x000000FF PCP 3
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@ -582,7 +582,7 @@ static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order,
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REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
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}
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/* Validate number of tags suppoted by device */
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/* Validate number of tags supported by device */
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#define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
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val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST);
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val &= 0xFF;
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@ -2536,7 +2536,7 @@ static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
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}
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/**
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* bnx2x_get_emac_base - retrive emac base address
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* bnx2x_get_emac_base - retrieve emac base address
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*
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* @bp: driver handle
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* @mdc_mdio_access: access type
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@ -3593,7 +3593,7 @@ static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
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u8 ret = 0;
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vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
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if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
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/* Update the advertised flow-controled of LD/LP in AN */
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/* Update the advertised flow-controlled of LD/LP in AN */
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if (phy->req_line_speed == SPEED_AUTO_NEG)
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bnx2x_ext_phy_update_adv_fc(phy, params, vars);
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/* But set the flow-control result as the requested one */
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@ -3743,7 +3743,7 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
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{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
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};
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DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
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/* Set to default registers that may be overriden by 10G force */
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/* Set to default registers that may be overridden by 10G force */
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for (i = 0; i < ARRAY_SIZE(reg_set); i++)
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bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
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reg_set[i].val);
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@ -5425,7 +5425,7 @@ static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
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/* Resolve from gp_status in case of AN complete and not sgmii */
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if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
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/* Update the advertised flow-controled of LD/LP in AN */
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/* Update the advertised flow-controlled of LD/LP in AN */
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if (phy->req_line_speed == SPEED_AUTO_NEG)
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bnx2x_update_adv_fc(phy, params, vars, gp_status);
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/* But set the flow-control result as the requested one */
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@ -12669,7 +12669,7 @@ static int bnx2x_set_mc_list(struct bnx2x *bp)
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if (rc)
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return rc;
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/* Override the curently configured set of mc filters */
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/* Override the currently configured set of mc filters */
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rc = bnx2x_config_mcast(bp, &rparam,
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BNX2X_MCAST_CMD_SET);
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if (rc < 0)
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@ -2236,7 +2236,7 @@ extern const u32 dmae_reg_go_c[];
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/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
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#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
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/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
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* future expansion) each priorty is to be mapped to. Bits 3:0 specify the
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* future expansion) each priority is to be mapped to. Bits 3:0 specify the
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* COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
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* priority field is extracted from the outer-most VLAN in receive packet.
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* Only COS 0 and COS 1 are supported in E2. */
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@ -2434,7 +2434,7 @@ extern const u32 dmae_reg_go_c[];
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/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
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#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
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/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
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* future expansion) each priorty is to be mapped to. Bits 3:0 specify the
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* future expansion) each priority is to be mapped to. Bits 3:0 specify the
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* COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
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* priority field is extracted from the outer-most VLAN in receive packet.
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* Only COS 0 and COS 1 are supported in E2. */
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|
|
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|
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@ -177,7 +177,7 @@ static void lio_cn66xx_setup_pkt_ctl_regs(struct octeon_device *oct)
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|
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/* 66XX SPECIFIC */
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if (CFG_GET_OQ_MAX_Q(cn6xxx->conf) <= 4)
|
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/* Disable RING_EN if only upto 4 rings are used. */
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/* Disable RING_EN if only up to 4 rings are used. */
|
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pktctl &= ~(1 << 4);
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else
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pktctl |= (1 << 4);
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|
|
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|
|
@ -565,7 +565,7 @@ static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs,
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}
|
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|
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/**
|
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* liquidio_push_packet - Routine to push packets arriving on Octeon interface upto network layer.
|
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* liquidio_push_packet - Routine to push packets arriving on Octeon interface up to network layer.
|
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* @octeon_id:octeon device id.
|
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* @skbuff: skbuff struct to be passed to network layer.
|
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* @len: size of total data received.
|
||||
|
|
|
|||
|
|
@ -254,7 +254,7 @@ struct octeon_oq_config {
|
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u64 pkts_per_intr:16;
|
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|
||||
/** Interrupt Coalescing (Time Interval). Octeon will interrupt the
|
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* host if atleast one packet was sent in the time interval specified
|
||||
* host if at least one packet was sent in the time interval specified
|
||||
* by this field. The driver uses time interval interrupt coalescing
|
||||
* by default. The time is specified in microseconds.
|
||||
*/
|
||||
|
|
@ -296,7 +296,7 @@ struct octeon_oq_config {
|
|||
u64 oq_intr_pkt:16;
|
||||
|
||||
/** Interrupt Coalescing (Time Interval). Octeon will interrupt the
|
||||
* host if atleast one packet was sent in the time interval specified
|
||||
* host if at least one packet was sent in the time interval specified
|
||||
* by this field. The driver uses time interval interrupt coalescing
|
||||
* by default. The time is specified in microseconds.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ struct oct_iq_stats {
|
|||
|
||||
/** The instruction (input) queue.
|
||||
* The input queue is used to post raw (instruction) mode data or packet
|
||||
* data to Octeon device from the host. Each input queue (upto 4) for
|
||||
* data to Octeon device from the host. Each input queue (up to 4) for
|
||||
* a Octeon device has one such structure to represent it.
|
||||
*/
|
||||
struct octeon_instr_queue {
|
||||
|
|
|
|||
|
|
@ -166,7 +166,7 @@ static inline int octeon_map_pci_barx(struct octeon_device *oct,
|
|||
* errno -EINTR: user abort the command.
|
||||
* errno -ETIME: user spefified timeout value has been expired.
|
||||
* errno -EBUSY: the response of the request does not return in
|
||||
* resonable time (LIO_SC_MAX_TMO_MS).
|
||||
* reasonable time (LIO_SC_MAX_TMO_MS).
|
||||
* the sc wll be move to zombie response list by
|
||||
* lio_process_ordered_list()
|
||||
*
|
||||
|
|
|
|||
|
|
@ -277,7 +277,7 @@ int octnet_send_nic_data_pkt(struct octeon_device *oct,
|
|||
|
||||
/** Send a NIC control packet to the device
|
||||
* @param oct - octeon device pointer
|
||||
* @param nctrl - control structure with command, timout, and callback info
|
||||
* @param nctrl - control structure with command, timeout, and callback info
|
||||
* @returns IQ_FAILED if it failed to add to the input queue. IQ_STOP if the
|
||||
* queue should be stopped, and IQ_SEND_OK if it sent okay.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ static void __check_db_timeout(struct octeon_device *oct, u64 iq_no);
|
|||
|
||||
static void (*reqtype_free_fn[MAX_OCTEON_DEVICES][REQTYPE_LAST + 1]) (void *);
|
||||
|
||||
/* Define this to return the request status comaptible to old code */
|
||||
/* Define this to return the request status compatible to old code */
|
||||
/*#define OCTEON_USE_OLD_REQ_STATUS*/
|
||||
|
||||
/* Return 0 on success, 1 on failure */
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@
|
|||
* This value ensures that once a packet has been "accepted"
|
||||
* for reception it will not get dropped due to non-availability
|
||||
* of CQ descriptor. An errata in HW mandates this value to be
|
||||
* atleast 0x100.
|
||||
* at least 0x100.
|
||||
*/
|
||||
#define NICPF_CQM_MIN_DROP_LEVEL 0x100
|
||||
|
||||
|
|
|
|||
|
|
@ -595,7 +595,7 @@ static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
|
|||
nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg);
|
||||
}
|
||||
|
||||
/* 4 level transmit side scheduler configutation
|
||||
/* 4 level transmit side scheduler configuration
|
||||
* for TNS bypass mode
|
||||
*
|
||||
* Sample configuration for SQ0 on 88xx
|
||||
|
|
|
|||
|
|
@ -373,7 +373,7 @@ static void de_rx_err_acct (struct de_private *de, unsigned rx_tail,
|
|||
rx_tail, status, len);
|
||||
|
||||
if ((status & 0x38000300) != 0x0300) {
|
||||
/* Ingore earlier buffers. */
|
||||
/* Ignore earlier buffers. */
|
||||
if ((status & 0xffff) != 0x7fff) {
|
||||
netif_warn(de, rx_err, de->dev,
|
||||
"Oversized Ethernet frame spanned multiple buffers, status %08x!\n",
|
||||
|
|
|
|||
|
|
@ -177,7 +177,7 @@ int tulip_poll(struct napi_struct *napi, int budget)
|
|||
pkt_len > 1518) {
|
||||
if ((status & (RxLengthOver2047 |
|
||||
RxWholePkt)) != RxWholePkt) {
|
||||
/* Ingore earlier buffers. */
|
||||
/* Ignore earlier buffers. */
|
||||
if ((status & 0xffff) != 0x7fff) {
|
||||
if (tulip_debug > 1)
|
||||
dev_warn(&dev->dev,
|
||||
|
|
@ -408,7 +408,7 @@ static int tulip_rx(struct net_device *dev)
|
|||
pkt_len > 1518) {
|
||||
if ((status & (RxLengthOver2047 |
|
||||
RxWholePkt)) != RxWholePkt) {
|
||||
/* Ingore earlier buffers. */
|
||||
/* Ignore earlier buffers. */
|
||||
if ((status & 0xffff) != 0x7fff) {
|
||||
if (tulip_debug > 1)
|
||||
netdev_warn(dev,
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
|
||||
/* Read and write the MII registers using software-generated serial
|
||||
MDIO protocol. It is just different enough from the EEPROM protocol
|
||||
to not share code. The maxium data clock rate is 2.5 Mhz. */
|
||||
to not share code. The maximum data clock rate is 2.5 Mhz. */
|
||||
#define MDIO_SHIFT_CLK 0x10000
|
||||
#define MDIO_DATA_WRITE0 0x00000
|
||||
#define MDIO_DATA_WRITE1 0x20000
|
||||
|
|
|
|||
|
|
@ -250,7 +250,7 @@ enum t21143_csr6_bits {
|
|||
csr6_ttm = (1<<22), /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
|
||||
csr6_sf = (1<<21), /* Store and forward. If set ignores TR bits */
|
||||
csr6_hbd = (1<<19), /* Heart beat disable. Disables SQE function in 10baseT */
|
||||
csr6_ps = (1<<18), /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
|
||||
csr6_ps = (1<<18), /* Port Select. 0 (default) = 10baseT, 1 = 100baseTX: can't be set */
|
||||
csr6_ca = (1<<17), /* Collision Offset Enable. If set uses special algorithm in low collision situations */
|
||||
csr6_trh = (1<<15), /* Transmit Threshold high bit */
|
||||
csr6_trl = (1<<14), /* Transmit Threshold low bit */
|
||||
|
|
@ -274,7 +274,7 @@ enum t21143_csr6_bits {
|
|||
csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
|
||||
csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
|
||||
/* set both and you get (PHY) loopback */
|
||||
csr6_fd = (1<<9), /* Full duplex mode, disables hearbeat, no loopback */
|
||||
csr6_fd = (1<<9), /* Full duplex mode, disables heartbeat, no loopback */
|
||||
csr6_pm = (1<<7), /* Pass All Multicast */
|
||||
csr6_pr = (1<<6), /* Promiscuous mode */
|
||||
csr6_sb = (1<<5), /* Start(1)/Stop(0) backoff counter */
|
||||
|
|
|
|||
|
|
@ -1188,7 +1188,7 @@ static int netdev_rx(struct net_device *dev)
|
|||
break;
|
||||
if ((status & 0x38008300) != 0x0300) {
|
||||
if ((status & 0x38000300) != 0x0300) {
|
||||
/* Ingore earlier buffers. */
|
||||
/* Ignore earlier buffers. */
|
||||
if ((status & 0xffff) != 0x7fff) {
|
||||
dev_warn(&dev->dev,
|
||||
"Oversized Ethernet frame spanned multiple buffers, entry %#x status %04x!\n",
|
||||
|
|
|
|||
|
|
@ -591,7 +591,7 @@ static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
|
|||
#define HILINK_ACCESS_SEL_CFG 0x40008
|
||||
/* hilink4 & hilink3 use the same xge training and
|
||||
* xge u adaptor. There is a hilink access sel cfg
|
||||
* register to select which one to be configed
|
||||
* register to select which one to be configured
|
||||
*/
|
||||
if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) &&
|
||||
(mac_cb->mac_id <= 3))
|
||||
|
|
|
|||
|
|
@ -139,7 +139,7 @@ static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
|
|||
}
|
||||
|
||||
/**
|
||||
* hns_ppe_checksum_hw - set ppe checksum caculate
|
||||
* hns_ppe_checksum_hw - set ppe checksum calculate
|
||||
* @ppe_cb: ppe device
|
||||
* @value: value
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1230,7 +1230,7 @@ static void hns_nic_update_stats(struct net_device *netdev)
|
|||
h->dev->ops->update_stats(h, &netdev->stats);
|
||||
}
|
||||
|
||||
/* set mac addr if it is configed. or leave it to the AE driver */
|
||||
/* set mac addr if it is configured. or leave it to the AE driver */
|
||||
static void hns_init_mac_addr(struct net_device *ndev)
|
||||
{
|
||||
struct hns_nic_priv *priv = netdev_priv(ndev);
|
||||
|
|
@ -2317,7 +2317,7 @@ static int hns_nic_dev_probe(struct platform_device *pdev)
|
|||
ret = device_property_read_u32(dev, "port-id", &port_id);
|
||||
if (ret)
|
||||
goto out_read_prop_fail;
|
||||
/* for old dts, we need to caculate the port offset */
|
||||
/* for old dts, we need to calculate the port offset */
|
||||
port_id = port_id < HNS_SRV_OFFSET ? port_id + HNS_DEBUG_OFFSET
|
||||
: port_id - HNS_SRV_OFFSET;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10522,7 +10522,7 @@ static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle,
|
|||
}
|
||||
|
||||
/* After disable sriov, VF still has some config and info need clean,
|
||||
* which configed by PF.
|
||||
* which configured by PF.
|
||||
*/
|
||||
static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ enum hclge_shaper_level {
|
|||
* IR(Mbps) = ------------------------- * CLOCK(1000Mbps)
|
||||
* Tick * (2 ^ IR_s)
|
||||
*
|
||||
* @return: 0: calculate sucessful, negative: fail
|
||||
* @return: 0: calculate successful, negative: fail
|
||||
*/
|
||||
static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
|
||||
struct hclge_shaper_ir_para *ir_para,
|
||||
|
|
|
|||
|
|
@ -1880,7 +1880,7 @@ static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
|
|||
* from PF as cmdq would be in unreliable state i.e. mailbox
|
||||
* communication between PF and VF would be broken.
|
||||
*
|
||||
* if we are never geting into pending state it means either:
|
||||
* if we are never getting into pending state it means either:
|
||||
* 1. PF is not receiving our request which could be due to IMP
|
||||
* reset
|
||||
* 2. PF is screwed
|
||||
|
|
|
|||
|
|
@ -729,7 +729,7 @@
|
|||
#define MVPP2_MAX_TXQ 8
|
||||
|
||||
/* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO
|
||||
* skb. As we need a maxium of two descriptors per fragments (1 header, 1 data),
|
||||
* skb. As we need a maximum of two descriptors per fragments (1 header, 1 data),
|
||||
* multiply this value by two to count the maximum number of skb descs needed.
|
||||
*/
|
||||
#define MVPP2_MAX_TSO_SEGS 300
|
||||
|
|
|
|||
|
|
@ -382,7 +382,7 @@ static int mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
|
|||
struct mvpp2_prs_entry pe;
|
||||
int tid;
|
||||
|
||||
/* Go through the all entires with MVPP2_PRS_LU_FLOWS */
|
||||
/* Go through the all entries with MVPP2_PRS_LU_FLOWS */
|
||||
for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
|
||||
u8 bits;
|
||||
|
||||
|
|
@ -1212,7 +1212,7 @@ static void mvpp2_prs_mh_init(struct mvpp2 *priv)
|
|||
mvpp2_prs_hw_write(priv, &pe);
|
||||
}
|
||||
|
||||
/* Set default entires (place holder) for promiscuous, non-promiscuous and
|
||||
/* Set default entries (place holder) for promiscuous, non-promiscuous and
|
||||
* multicast MAC addresses
|
||||
*/
|
||||
static void mvpp2_prs_mac_init(struct mvpp2 *priv)
|
||||
|
|
@ -2241,7 +2241,7 @@ mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
|
|||
struct mvpp2_prs_entry pe;
|
||||
int tid;
|
||||
|
||||
/* Go through the all entires with MVPP2_PRS_LU_MAC */
|
||||
/* Go through the all entries with MVPP2_PRS_LU_MAC */
|
||||
for (tid = MVPP2_PE_MAC_RANGE_START;
|
||||
tid <= MVPP2_PE_MAC_RANGE_END; tid++) {
|
||||
unsigned int entry_pmap;
|
||||
|
|
@ -2539,7 +2539,7 @@ int mvpp2_prs_def_flow(struct mvpp2_port *port)
|
|||
|
||||
/* Such entry not exist */
|
||||
if (tid < 0) {
|
||||
/* Go through the all entires from last to first */
|
||||
/* Go through the all entries from last to first */
|
||||
tid = mvpp2_prs_tcam_first_free(port->priv,
|
||||
MVPP2_PE_LAST_FREE_TID,
|
||||
MVPP2_PE_FIRST_FREE_TID);
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@ enum npc_kpu_lc_ltype {
|
|||
NPC_LT_LC_CUSTOM1 = 0xF,
|
||||
};
|
||||
|
||||
/* Don't modify Ltypes upto SCTP, otherwise it will
|
||||
/* Don't modify Ltypes up to SCTP, otherwise it will
|
||||
* effect flow tag calculation and thus RSS.
|
||||
*/
|
||||
enum npc_kpu_ld_ltype {
|
||||
|
|
@ -140,7 +140,7 @@ enum npc_kpu_lg_ltype {
|
|||
NPC_LT_LG_CUSTOM1 = 0xF,
|
||||
};
|
||||
|
||||
/* Don't modify Ltypes upto SCTP, otherwise it will
|
||||
/* Don't modify Ltypes up to SCTP, otherwise it will
|
||||
* effect flow tag calculation and thus RSS.
|
||||
*/
|
||||
enum npc_kpu_lh_ltype {
|
||||
|
|
|
|||
|
|
@ -4974,7 +4974,7 @@ static void rvu_nix_setup_capabilities(struct rvu *rvu, int blkaddr)
|
|||
|
||||
/* On OcteonTx2 DWRR quantum is directly configured into each of
|
||||
* the transmit scheduler queues. And PF/VF drivers were free to
|
||||
* config any value upto 2^24.
|
||||
* config any value up to 2^24.
|
||||
* On CN10K, HW is modified, the quantum configuration at scheduler
|
||||
* queues is in terms of weight. And SW needs to setup a base DWRR MTU
|
||||
* at NIX_AF_DWRR_RPM_MTU / NIX_AF_DWRR_SDP_MTU. HW will do
|
||||
|
|
|
|||
|
|
@ -301,7 +301,7 @@ static void cn10k_get_ingress_rate_cfg(u64 rate, u32 *rate_exp,
|
|||
* policer timeunit * 2^rdiv ie 2 * 2^rdiv usecs, to the token bucket.
|
||||
* Here policer timeunit is 2 usecs and rate is in bits per sec.
|
||||
* Since floating point cannot be used below algorithm uses 1000000
|
||||
* scale factor to support rates upto 100Gbps.
|
||||
* scale factor to support rates up to 100Gbps.
|
||||
*/
|
||||
tmp = rate * 32 * 2;
|
||||
if (tmp < 256000000) {
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ static int otx2_pfc_txschq_alloc_one(struct otx2_nic *pfvf, u8 prio)
|
|||
if (!req)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Request one schq per level upto max level as configured
|
||||
/* Request one schq per level up to max level as configured
|
||||
* link config level. These rest of the scheduler can be
|
||||
* same as hw.txschq_list.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -514,7 +514,7 @@ static int add_del_hash_entry(struct pxa168_eth_private *pep,
|
|||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* Create an addressTable entry from MAC address info
|
||||
* found in the specifed net_device struct
|
||||
* found in the specified net_device struct
|
||||
*
|
||||
* Input : pointer to ethernet interface network device structure
|
||||
* Output : N/A
|
||||
|
|
@ -806,7 +806,7 @@ static int rxq_process(struct net_device *dev, int budget)
|
|||
stats->rx_bytes += rx_desc->byte_cnt;
|
||||
/*
|
||||
* In case received a packet without first / last bits on OR
|
||||
* the error summary bit is on, the packets needs to be droped.
|
||||
* the error summary bit is on, the packets needs to be dropped.
|
||||
*/
|
||||
if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
|
||||
(RX_FIRST_DESC | RX_LAST_DESC))
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ netxen_poll_rsp(struct netxen_adapter *adapter)
|
|||
int timeout = 0;
|
||||
|
||||
do {
|
||||
/* give atleast 1ms for firmware to respond */
|
||||
/* give at least 1ms for firmware to respond */
|
||||
msleep(1);
|
||||
|
||||
if (++timeout > NX_OS_CRB_RETRY_COUNT)
|
||||
|
|
|
|||
|
|
@ -561,7 +561,7 @@ int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *line_count)
|
|||
* block in the ILT client. This is later used to
|
||||
* configure the CDU segment offset registers and
|
||||
* results in an FL command for TIDs of this
|
||||
* segement behaves as regular load commands
|
||||
* segment behaves as regular load commands
|
||||
* (loading TIDs from the working memory).
|
||||
*/
|
||||
line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
|
||||
|
|
|
|||
|
|
@ -783,7 +783,7 @@ struct qed_mcp_info {
|
|||
u16 mfw_mb_length;
|
||||
u32 mcp_hist;
|
||||
|
||||
/* Capabilties negotiated with the MFW */
|
||||
/* Capabilities negotiated with the MFW */
|
||||
u32 capabilities;
|
||||
|
||||
/* S/N for debug data mailbox commands */
|
||||
|
|
|
|||
|
|
@ -909,7 +909,7 @@ struct qlcnic_mac_vlan_list {
|
|||
|
||||
#define QLCNIC_LRO_REQUEST_CLEANUP 4
|
||||
|
||||
/* Capabilites received */
|
||||
/* Capabilities received */
|
||||
#define QLCNIC_FW_CAPABILITY_TSO BIT_1
|
||||
#define QLCNIC_FW_CAPABILITY_BDG BIT_8
|
||||
#define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
|
||||
|
|
|
|||
|
|
@ -1957,9 +1957,9 @@ static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
|
|||
* qlcnic_83xx_exec_template_cmd
|
||||
*
|
||||
* @p_dev: adapter structure
|
||||
* @p_buff: Poiter to instruction template
|
||||
* @p_buff: Pointer to instruction template
|
||||
*
|
||||
* Template provides instructions to stop, restart and initalize firmware.
|
||||
* Template provides instructions to stop, restart and initialize firmware.
|
||||
* These instructions are abstracted as a series of read, write and
|
||||
* poll operations on hardware registers. Register information and operation
|
||||
* specifics are not exposed to the driver. Driver reads the template from
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
|
|||
int timeout = 0, err = 0;
|
||||
|
||||
do {
|
||||
/* give atleast 1ms for firmware to respond */
|
||||
/* give at least 1ms for firmware to respond */
|
||||
mdelay(1);
|
||||
|
||||
if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
|
||||
|
|
|
|||
|
|
@ -640,7 +640,7 @@ static int qlcnic_max_rings(struct qlcnic_adapter *adapter, u8 ring_cnt,
|
|||
|
||||
void qlcnic_set_tx_ring_count(struct qlcnic_adapter *adapter, u8 tx_cnt)
|
||||
{
|
||||
/* 83xx adapter does not have max_tx_rings intialized in probe */
|
||||
/* 83xx adapter does not have max_tx_rings initialized in probe */
|
||||
if (adapter->max_tx_rings)
|
||||
adapter->drv_tx_rings = qlcnic_max_rings(adapter, tx_cnt,
|
||||
QLCNIC_TX_QUEUE);
|
||||
|
|
@ -650,7 +650,7 @@ void qlcnic_set_tx_ring_count(struct qlcnic_adapter *adapter, u8 tx_cnt)
|
|||
|
||||
void qlcnic_set_sds_ring_count(struct qlcnic_adapter *adapter, u8 rx_cnt)
|
||||
{
|
||||
/* 83xx adapter does not have max_sds_rings intialized in probe */
|
||||
/* 83xx adapter does not have max_sds_rings initialized in probe */
|
||||
if (adapter->max_sds_rings)
|
||||
adapter->drv_sds_rings = qlcnic_max_rings(adapter, rx_cnt,
|
||||
QLCNIC_RX_QUEUE);
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* Hardware independent state machine implemantation
|
||||
* Hardware independent state machine implementation
|
||||
* The following external SMT functions are referenced :
|
||||
*
|
||||
* queue_event()
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* Hardware independent state machine implemantation
|
||||
* Hardware independent state machine implementation
|
||||
* The following external SMT functions are referenced :
|
||||
*
|
||||
* queue_event()
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ static u_long read_mdr(struct s_smc *smc, unsigned int addr)
|
|||
CHECK_NPP() ;
|
||||
MARR(addr) ;
|
||||
outpw(FM_A(FM_CMDREG1),FM_IRMEMWO) ;
|
||||
CHECK_NPP() ; /* needed for PCI to prevent from timeing violations */
|
||||
CHECK_NPP() ; /* needed for PCI to prevent from timing violations */
|
||||
/* p = MDRR() ; */ /* bad read values if the workaround */
|
||||
/* smc->hw.mc_dummy = *((short volatile far *)(addr)))*/
|
||||
/* is used */
|
||||
|
|
@ -572,7 +572,7 @@ Note After any ring operational change the transmit complete
|
|||
The operating system dependent module must enable
|
||||
the transmit complete interrupt of a queue,
|
||||
- when it queues the first frame,
|
||||
because of no transmit resources are beeing
|
||||
because of no transmit resources are being
|
||||
available and
|
||||
- when it escapes from the function llc_restart_tx
|
||||
while some frames are still queued.
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ struct hw_modul {
|
|||
struct s_mbuf_pool mbuf_pool ;
|
||||
struct hwm_r r ;
|
||||
|
||||
union s_fp_descr volatile *descr_p ; /* points to the desriptor area */
|
||||
union s_fp_descr volatile *descr_p ; /* points to the descriptor area */
|
||||
|
||||
u_short pass_SMT ; /* pass SMT frames */
|
||||
u_short pass_NSA ; /* pass all NSA frames */
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ struct s_sba {
|
|||
long msg_mib_ov ; /* Current Overhead for this Path*/
|
||||
long msg_category ; /* Category of the Allocation */
|
||||
u_long msg_max_t_neg ; /* longest T_Neg acceptable */
|
||||
u_long msg_min_seg_siz ; /* minimum segement size */
|
||||
u_long msg_min_seg_siz ; /* minimum segment size */
|
||||
struct smt_header *sm ; /* points to the rec message */
|
||||
struct fddi_addr *msg_alloc_addr ; /* Allocation Address */
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* Hardware independent state machine implemantation
|
||||
* Hardware independent state machine implementation
|
||||
* The following external SMT functions are referenced :
|
||||
*
|
||||
* queue_event()
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* Hardware independent state machine implemantation
|
||||
* Hardware independent state machine implementation
|
||||
* The following external SMT functions are referenced :
|
||||
*
|
||||
* queue_event()
|
||||
|
|
|
|||
|
|
@ -193,7 +193,7 @@ void llc_conn_rtn_pdu(struct sock *sk, struct sk_buff *skb)
|
|||
}
|
||||
|
||||
/**
|
||||
* llc_conn_resend_i_pdu_as_cmd - resend all all unacknowledged I PDUs
|
||||
* llc_conn_resend_i_pdu_as_cmd - resend all unacknowledged I PDUs
|
||||
* @sk: active connection
|
||||
* @nr: NR
|
||||
* @first_p_bit: p_bit value of first pdu
|
||||
|
|
|
|||
|
|
@ -242,7 +242,7 @@ check_exceptions()
|
|||
echo "PASS: ping to .254 bypassed ipsec tunnel ($logpostfix)"
|
||||
fi
|
||||
|
||||
# ping to .253 should use use ipsec due to direct policy exception.
|
||||
# ping to .253 should use ipsec due to direct policy exception.
|
||||
check_xfrm 1 253
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "FAIL: expected ping to .253 to use ipsec tunnel ($logpostfix)"
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user