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TI K3 device tree updates for v6.20

Browse Source 
Generic Fixes/Cleanups:
 - Minor whitespace cleanup and lowercase hex formatting for consistency
 - Various DT schema warning fixes across multiple boards
 
 SoC Specific Features and Fixes:
 AM62P/J722S:
 - Add HSM M4F node for hardware security module support
 
 J784S4/J742S2/J721S2:
 - Add HSM M4F node for hardware security module support
 - Refactor watchdog instances for j784s4
 - Move c71_3 node to appropriate order in device tree
 
 Board Specific Fixes:
 AM62:
 - phycore-som: Add bootphase tags to cpsw_mac_syscon and phy_gmii_sel
 
 AM62A:
 - phycore-som: Add bootphase tags to cpsw_mac_syscon and phy_gmii_sel
 
 AM62P:
 - Verdin: Fix SD regulator startup delay
 
 AM67A:
 - Kontron SA67: Fix CMA node and SD card regulator configuration
 
 AM69:
 - Aquila: Change main_spi0/2 chip select to GPIO mode
 - Aquila-clover: Change main_spi2 CS0 to GPIO mode
 - Aquila-dev/clover: Fix USB-C Sink PDO configuration
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Merge tag 'ti-k3-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt

TI K3 device tree updates for v6.20

Generic Fixes/Cleanups:
- Minor whitespace cleanup and lowercase hex formatting for consistency
- Various DT schema warning fixes across multiple boards

SoC Specific Features and Fixes:
AM62P/J722S:
- Add HSM M4F node for hardware security module support

J784S4/J742S2/J721S2:
- Add HSM M4F node for hardware security module support
- Refactor watchdog instances for j784s4
- Move c71_3 node to appropriate order in device tree

Board Specific Fixes:
AM62:
- phycore-som: Add bootphase tags to cpsw_mac_syscon and phy_gmii_sel

AM62A:
- phycore-som: Add bootphase tags to cpsw_mac_syscon and phy_gmii_sel

AM62P:
- Verdin: Fix SD regulator startup delay

AM67A:
- Kontron SA67: Fix CMA node and SD card regulator configuration

AM69:
- Aquila: Change main_spi0/2 chip select to GPIO mode
- Aquila-clover: Change main_spi2 CS0 to GPIO mode
- Aquila-dev/clover: Fix USB-C Sink PDO configuration

* tag 'ti-k3-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
  arm64: dts: ti: k3-am67a-kontron-sa67-base: Fix SD card regulator
  arm64: dts: ti: k3-am67a-kontron-sa67-base: Fix CMA node
  arm64: dts: ti: k3-am62p-j722s-common-main: Add HSM M4F node
  arm64: dts: ti: k3-{j784s4-j742s2/j721s2}-mcu-wakeup: Add HSM M4F node
  arm64: dts: ti: k3-j784s4-j742s2-main-common.dtsi: Refactor watchdog instances for j784s4
  arm64: dts: ti: k3-j784s4-main.dtsi: Move c71_3 node to appropriate order
  arm64: dts: ti: k3-am69-aquila-clover: Change main_spi2 CS0 to GPIO mode
  arm64: dts: ti: k3-am69-aquila: Change main_spi0/2 CS to GPIO mode
  arm64: dts: ti: Use lowercase hex
  arm64: dts: ti: Minor whitespace cleanup
  arm64: dts: ti: am62p-verdin: Fix SD regulator startup delay
  arm64: dts: ti: k3-am69-aquila-clover: Fix USB-C Sink PDO
  arm64: dts: ti: k3-am69-aquila-dev: Fix USB-C Sink PDO
  arm64: dts: ti: k3-am62(a)-phycore-som: Add bootphase tag to phy_gmii_sel
  arm64: dts: ti: k3-am62a-phycore-som: Add bootphase tag to cpsw_mac_syscon
  arm64: dts: ti: k3-am62-phycore-som: Add bootphase tag to cpsw_mac_syscon
  arm64: dts: ti: k3-am62-lp-sk-nand: Rename pinctrls to fix schema warnings
  arm64: dts: ti: k3-am642-phyboard-electra-x27-gpio1-spi1-uart3: Fix schema warnings
  arm64: dts: ti: k3-am642-phyboard-electra-peb-c-010: Fix icssg-prueth schema warning

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-01-29 11:13:45 +01:00
commit 0a82d3d407
35 changed files with 238 additions and 160 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso
View File

@ -14,7 +14,7 @@ &mcasp1 {
};
&main_pmx0 {
gpmc0_pins_default: gpmc0-pins-default {
gpmc0_pins_default: gpmc0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */

8
arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
View File

@ -220,6 +220,10 @@ &cpsw_port1 {
bootph-all;
};
&cpsw_mac_syscon {
bootph-all;
};
&cpsw3g_mdio {
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
@ -359,6 +363,10 @@ serial_flash: flash@0 {
};
};
&phy_gmii_sel {
bootph-all;
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;

8
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
View File

@ -197,6 +197,10 @@ &cpsw_port1 {
bootph-all;
};
&cpsw_mac_syscon {
bootph-all;
};
&cpsw3g_mdio {
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
@ -350,6 +354,10 @@ serial_flash: flash@0 {
};
};
&phy_gmii_sel {
bootph-all;
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;

2
arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
View File

@ -669,7 +669,7 @@ &ospi0 {
pinctrl-0 = <&ospi0_pins_default>;
status = "okay";
flash@0{
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;

17
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
View File

@ -1117,4 +1117,21 @@ vpu: video-codec@30210000 {
clocks = <&k3_clks 204 2>;
power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
};
hsm: remoteproc@43c00000 {
compatible = "ti,hsm-m4fss";
/* contiguous regions but instantiated separately in HW */
reg = <0x00 0x43c00000 0x00 0x20000>,
<0x00 0x43c20000 0x00 0x10000>,
<0x00 0x43c30000 0x00 0x10000>;
reg-names = "sram0_0", "sram0_1", "sram1";
resets = <&k3_reset 225 1>;
firmware-name = "am62p-hsm-m4f-fw";
bootph-pre-ram;
ti,sci = <&dmsc>;
ti,sci-dev-id = <225>;
ti,sci-proc-ids = <0x80 0xff>;
/* reserved for early-stage bootloader */
status = "reserved";
};
};

4
arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
View File

@ -112,7 +112,7 @@ reg_sd1_vmmc: regulator-sdhci1-vmmc {
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SD";
startup-delay-us = <2000>;
startup-delay-us = <20000>;
};
reg_sd1_vqmmc: regulator-sdhci1-vqmmc {
@ -514,7 +514,7 @@ pinctrl_sdhci2: main-mmc2-default-pins {
pinctrl-single,pins = <
AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ /* SODIMM 160, WiFi_SDIO_CMD */
AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ /* SODIMM 156, WiFi_SDIO_CLK */
AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */
AM62PX_IOPAD(0x011c, PIN_INPUT, 0) /* () MMC2_CLKLB */
AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ /* SODIMM 162, WiFi_SDIO_DATA0 */
AM62PX_IOPAD(0x0110, PIN_INPUT, 0) /* (K22) MMC2_DAT1 */ /* SODIMM 164, WiFi_SDIO_DATA1 */
AM62PX_IOPAD(0x010c, PIN_INPUT, 0) /* (L20) MMC2_DAT2 */ /* SODIMM 166, WiFi_SDIO_DATA2 */

1
arch/arm64/boot/dts/ti/k3-am62p.dtsi
View File

@ -96,6 +96,7 @@ cbass_main: bus@f0000 {
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
<0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */

2
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
View File

@ -283,7 +283,7 @@ main_mmc2_pins_default: main-mmc2-default-pins {
pinctrl-single,pins = <
AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */
AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */
AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */
AM62PX_IOPAD(0x011c, PIN_INPUT, 0) /* () MMC2_CLKLB */
AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */
AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */

4
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
View File

@ -224,7 +224,7 @@ &dphy0 {
status = "okay";
};
&main_i2c0{
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clock-frequency = <400000>;
@ -466,7 +466,7 @@ &sdhci1 {
pinctrl-0 = <&pinctrl_mmc1>;
disable-wp;
bootph-all;
status="okay";
status = "okay";
};
&ti_csi2rx0 {

18
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
View File

@ -84,7 +84,7 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01840000 0x00 0xC0000>, /* GICR */
<0x00 0x01840000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */
@ -685,14 +685,14 @@ cpsw3g: ethernet@8000000 {
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
dmas = <&main_pktdma 0xC500 15>,
<&main_pktdma 0xC501 15>,
<&main_pktdma 0xC502 15>,
<&main_pktdma 0xC503 15>,
<&main_pktdma 0xC504 15>,
<&main_pktdma 0xC505 15>,
<&main_pktdma 0xC506 15>,
<&main_pktdma 0xC507 15>,
dmas = <&main_pktdma 0xc500 15>,
<&main_pktdma 0xc501 15>,
<&main_pktdma 0xc502 15>,
<&main_pktdma 0xc503 15>,
<&main_pktdma 0xc504 15>,
<&main_pktdma 0xc505 15>,
<&main_pktdma 0xc506 15>,
<&main_pktdma 0xc507 15>,
<&main_pktdma 0x4500 15>;
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
"tx7", "rx";

7
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso
View File

@ -30,13 +30,10 @@ icssg1-ethernet {
<&main_pktdma 0xc206 15>, /* egress slice 1 */
<&main_pktdma 0xc207 15>, /* egress slice 1 */
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
<&main_pktdma 0x4201 15>, /* ingress slice 1 */
<&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
<&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
<&main_pktdma 0x4201 15>; /* ingress slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1",
"rxmgm0", "rxmgm1";
"rx0", "rx1";
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",

6
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
View File

@ -206,8 +206,8 @@ icssg0_mdio_pins_default: icssg0-mdio-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
AM64X_IOPAD(0x01A8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
AM64X_IOPAD(0x01AC, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
AM64X_IOPAD(0x01a8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
AM64X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
>;
};
@ -300,7 +300,7 @@ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;

12
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso
View File

@ -20,22 +20,22 @@ aliases {
};
&main_pmx0 {
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-pins-default {
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */
>;
};
main_spi1_pins_default: main-spi1-pins-default {
main_spi1_pins_default: main-spi1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */
AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
AM64X_IOPAD(0x021c, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
AM64X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (B15) SPI1_D0 */
AM64X_IOPAD(0x022C, PIN_INPUT, 0) /* (A15) SPI1_D1 */
AM64X_IOPAD(0x022c, PIN_INPUT, 0) /* (A15) SPI1_D1 */
>;
};
main_uart3_pins_default: main-uart3-pins-default {
main_uart3_pins_default: main-uart3-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */
AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */
@ -52,7 +52,7 @@ &main_gpio1 {
&main_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&main_spi1_pins_default>;
ti,pindir-d0-out-d1-in = <1>;
ti,pindir-d0-out-d1-in;
status = "okay";
};

58
arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi
View File

@ -138,28 +138,28 @@ AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7)
d2_uart0_ctsn: d2-uart0-ctsn-pins {
pinctrl-single,pins = <
/* (P1) MCU_UART0_CTSn */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4)
AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 4)
>;
};
d2_gpio: d2-gpio-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7)
>;
};
d2_gpio_pullup: d2-gpio-pullup-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7)
>;
};
d2_gpio_pulldown: d2-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7)
AM65X_WKUP_IOPAD(0x004c, PIN_INPUT_PULLDOWN, 7)
>;
};
@ -348,42 +348,42 @@ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7)
a2_gpio: a2-gpio-pins {
pinctrl-single,pins = <
/* (L5) WKUP_GPIO0_43 */
AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 7)
>;
};
a2_gpio_pullup: a2-gpio-pullup-pins {
pinctrl-single,pins = <
/* (L5) WKUP_GPIO0_43 */
AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 7)
>;
};
a2_gpio_pulldown: a2-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (L5) WKUP_GPIO0_43 */
AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7)
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT_PULLDOWN, 7)
>;
};
a3_gpio: a3-gpio-pins {
pinctrl-single,pins = <
/* (M5) WKUP_GPIO0_39 */
AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
AM65X_WKUP_IOPAD(0x006c, PIN_INPUT, 7)
>;
};
a3_gpio_pullup: a3-gpio-pullup-pins {
pinctrl-single,pins = <
/* (M5) WKUP_GPIO0_39 */
AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
AM65X_WKUP_IOPAD(0x006c, PIN_INPUT, 7)
>;
};
a3_gpio_pulldown: a3-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (M5) WKUP_GPIO0_39 */
AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7)
AM65X_WKUP_IOPAD(0x006c, PIN_INPUT_PULLDOWN, 7)
>;
};
@ -411,21 +411,21 @@ AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7)
a5_gpio: a5-gpio-pins {
pinctrl-single,pins = <
/* (N5) WKUP_GPIO0_35 */
AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7)
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 7)
>;
};
a5_gpio_pullup: a5-gpio-pullup-pins {
pinctrl-single,pins = <
/* (N5) WKUP_GPIO0_35 */
AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7)
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT_PULLUP, 7)
>;
};
a5_gpio_pulldown: a5-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (N5) WKUP_GPIO0_35 */
AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7)
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT_PULLDOWN, 7)
>;
};
@ -533,28 +533,28 @@ AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7)
d5_ehrpwm1_a: d5-ehrpwm1-a-pins {
pinctrl-single,pins = <
/* (AF17) EHRPWM1_A */
AM65X_IOPAD(0x008C, PIN_OUTPUT, 5)
AM65X_IOPAD(0x008c, PIN_OUTPUT, 5)
>;
};
d5_gpio: d5-gpio-pins {
pinctrl-single,pins = <
/* (AF17) GPIO0_35 */
AM65X_IOPAD(0x008C, PIN_INPUT, 7)
AM65X_IOPAD(0x008c, PIN_INPUT, 7)
>;
};
d5_gpio_pullup: d5-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AF17) GPIO0_35 */
AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7)
AM65X_IOPAD(0x008c, PIN_INPUT_PULLUP, 7)
>;
};
d5_gpio_pulldown: d5-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AF17) GPIO0_35 */
AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7)
AM65X_IOPAD(0x008c, PIN_INPUT_PULLDOWN, 7)
>;
};
@ -589,84 +589,84 @@ AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7)
d7_ehrpwm3_a: d7-ehrpwm3-a-pins {
pinctrl-single,pins = <
/* (AH15) EHRPWM3_A */
AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5)
AM65X_IOPAD(0x00ac, PIN_OUTPUT, 5)
>;
};
d7_gpio: d7-gpio-pins {
pinctrl-single,pins = <
/* (AH15) GPIO0_43 */
AM65X_IOPAD(0x00AC, PIN_INPUT, 7)
AM65X_IOPAD(0x00ac, PIN_INPUT, 7)
>;
};
d7_gpio_pullup: d7-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AH15) GPIO0_43 */
AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7)
AM65X_IOPAD(0x00ac, PIN_INPUT_PULLUP, 7)
>;
};
d7_gpio_pulldown: d7-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AH15) GPIO0_43 */
AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7)
AM65X_IOPAD(0x00ac, PIN_INPUT_PULLDOWN, 7)
>;
};
d8_ehrpwm4_a: d8-ehrpwm4-a-pins {
pinctrl-single,pins = <
/* (AG15) EHRPWM4_A */
AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5)
AM65X_IOPAD(0x00c0, PIN_OUTPUT, 5)
>;
};
d8_gpio: d8-gpio-pins {
pinctrl-single,pins = <
/* (AG15) GPIO0_48 */
AM65X_IOPAD(0x00C0, PIN_INPUT, 7)
AM65X_IOPAD(0x00c0, PIN_INPUT, 7)
>;
};
d8_gpio_pullup: d8-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AG15) GPIO0_48 */
AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7)
AM65X_IOPAD(0x00c0, PIN_INPUT_PULLUP, 7)
>;
};
d8_gpio_pulldown: d8-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AG15) GPIO0_48 */
AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7)
AM65X_IOPAD(0x00c0, PIN_INPUT_PULLDOWN, 7)
>;
};
d9_ehrpwm5_a: d9-ehrpwm5-a-pins {
pinctrl-single,pins = <
/* (AD15) EHRPWM5_A */
AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5)
AM65X_IOPAD(0x00cc, PIN_OUTPUT, 5)
>;
};
d9_gpio: d9-gpio-pins {
pinctrl-single,pins = <
/* (AD15) GPIO0_51 */
AM65X_IOPAD(0x00CC, PIN_INPUT, 7)
AM65X_IOPAD(0x00cc, PIN_INPUT, 7)
>;
};
d9_gpio_pullup: d9-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AD15) GPIO0_51 */
AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7)
AM65X_IOPAD(0x00cc, PIN_INPUT_PULLUP, 7)
>;
};
d9_gpio_pulldown: d9-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AD15) GPIO0_51 */
AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7)
AM65X_IOPAD(0x00cc, PIN_INPUT_PULLDOWN, 7)
>;
};
};

2
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
View File

@ -266,7 +266,7 @@ AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
minipcie_pins_default: minipcie-default-pins {
pinctrl-single,pins = <
/* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
AM65X_WKUP_IOPAD(0x003c, PIN_OUTPUT, 7)
>;
};
};

4
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
View File

@ -884,7 +884,7 @@ pcie0_rc: pcie@5500000 {
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
<0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
<0x82000000 0 0x10030000 0x0 0x10030000 0 0x07fd0000>;
ti,syscon-pcie-id = <&scm_conf 0x210>;
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
bus-range = <0x0 0xff>;
@ -905,7 +905,7 @@ pcie1_rc: pcie@5600000 {
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
<0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
<0x82000000 0 0x18030000 0x0 0x18030000 0 0x07fd0000>;
ti,syscon-pcie-id = <&scm_conf 0x210>;
ti,syscon-pcie-mode = <&scm_conf 0x4070>;
bus-range = <0x0 0xff>;

2
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
View File

@ -190,7 +190,7 @@ mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
>;
bootph-all;

4
arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
View File

@ -85,8 +85,7 @@ reserved_memory: reserved-memory {
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x10000000>;
alignment = <0x2000>;
size = <0x00 0x10000000>;
linux,cma-default;
};
@ -174,6 +173,7 @@ vcc_3p3_sd_vio_s0: regulator-6 {
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3p3_s0>;
regulator-boot-on;
enable-active-high;
enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>;
gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
states = <3300000 0x0>,

14
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
View File

@ -359,15 +359,15 @@ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
@ -392,7 +392,7 @@ J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
>;
};
@ -422,13 +422,13 @@ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
J721S2_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
J721S2_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
J721S2_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
>;
};

7
arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts
View File

@ -208,7 +208,8 @@ &main_spi2 {
pinctrl-0 = <&pinctrl_main_spi2>,
<&pinctrl_main_spi2_cs0>,
<&pinctrl_gpio_05>;
cs-gpios = <0>, <&wkup_gpio0 29 GPIO_ACTIVE_LOW>;
cs-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>,
<&wkup_gpio0 29 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
@ -280,8 +281,8 @@ connector {
try-power-role = "sink";
self-powered;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <1000000>;
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <0>;
ports {
#address-cells = <1>;

4
arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts
View File

@ -399,8 +399,8 @@ connector {
try-power-role = "sink";
self-powered;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <1000000>;
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <0>;
ports {
#address-cells = <1>;

6
arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi
View File

@ -479,7 +479,7 @@ J784S4_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (AM36) SPI0_D1 */ /* AQUILA D17 */
/* Aquila SPI_2 CS */
pinctrl_main_spi0_cs0: main-spi0-cs0-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (AM37) SPI0_CS0 */ /* AQUILA D16 */
J784S4_IOPAD(0x0cc, PIN_OUTPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ /* AQUILA D16 */
>;
};
@ -495,7 +495,7 @@ J784S4_IOPAD(0x0ac, PIN_OUTPUT, 10) /* (AE34) MCASP0_AXR15.SPI2_D1 */ /* AQUILA
/* Aquila SPI_1 CS */
pinctrl_main_spi2_cs0: main-spi2-cs0-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x09c, PIN_OUTPUT, 10) /* (AF35) MCASP0_AXR11.SPI2_CS1 */ /* AQUILA D9 */
J784S4_IOPAD(0x09c, PIN_OUTPUT, 7) /* (AF35) MCASP0_AXR11.GPIO0_39 */ /* AQUILA D9 */
>;
};
@ -1204,6 +1204,7 @@ &main_sdhci1 {
&main_spi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_main_spi0>, <&pinctrl_main_spi0_cs0>;
cs-gpios = <&main_gpio0 51 GPIO_ACTIVE_LOW>;
status = "disabled";
};
@ -1211,6 +1212,7 @@ &main_spi0 {
&main_spi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>;
cs-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>;
status = "disabled";
};

26
arch/arm64/boot/dts/ti/k3-am69-sk.dts
View File

@ -264,24 +264,24 @@ J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
J784S4_IOPAD(0x0c4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
>;
};
rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
J784S4_IOPAD(0x06c, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
J784S4_IOPAD(0x0b4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
J784S4_IOPAD(0x00c, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
J784S4_IOPAD(0x0b8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */
J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
J784S4_IOPAD(0x0a8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
J784S4_IOPAD(0x0a4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */
J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
J784S4_IOPAD(0x0cc, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
J784S4_IOPAD(0x08c, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
>;
@ -347,8 +347,8 @@ J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */
main_mcan7_pins_default: main-mcan7-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */
J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */
J784S4_IOPAD(0x0a0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */
J784S4_IOPAD(0x09c, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */
>;
};

4
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
View File

@ -212,7 +212,7 @@ mcu_timerio_input: pinctrl@40f04200 {
reg = <0x0 0x40f04200 0x0 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000F>;
pinctrl-single,function-mask = <0x0000000f>;
status = "reserved";
};
@ -222,7 +222,7 @@ mcu_timerio_output: pinctrl@40f04280 {
reg = <0x0 0x40f04280 0x0 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000F>;
pinctrl-single,function-mask = <0x0000000f>;
status = "reserved";
};

24
arch/arm64/boot/dts/ti/k3-j721e-sk.dts
View File

@ -443,29 +443,29 @@ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
J721E_IOPAD(0x01c, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
J721E_IOPAD(0x02c, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
J721E_IOPAD(0x1b0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
J721E_IOPAD(0x1d0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
J721E_IOPAD(0x11c, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
J721E_IOPAD(0x19c, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
J721E_IOPAD(0x00c, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
J721E_IOPAD(0x17c, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
J721E_IOPAD(0x18c, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
>;
};

4
arch/arm64/boot/dts/ti/k3-j721e.dtsi
View File

@ -41,7 +41,7 @@ cpu0: cpu@0 {
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
@ -55,7 +55,7 @@ cpu1: cpu@1 {
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;

19
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
View File

@ -87,7 +87,7 @@ wkup_pmx0: pinctrl@4301c000 {
wkup_pmx1: pinctrl@4301c038 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c038 0x00 0x02C>;
reg = <0x00 0x4301c038 0x00 0x02c>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
@ -766,4 +766,21 @@ mcu_watchdog1: watchdog@40610000 {
/* reserved for MCU_R5F0_1 */
status = "reserved";
};
hsm: remoteproc@43c00000 {
compatible = "ti,hsm-m4fss";
/* contiguous regions but instantiated separately in HW */
reg = <0x00 0x43c00000 0x00 0x20000>,
<0x00 0x43c20000 0x00 0x10000>,
<0x00 0x43c30000 0x00 0x10000>;
reg-names = "sram0_0", "sram0_1", "sram1";
resets = <&k3_reset 304 1>;
firmware-name = "j721s2-hsm-m4f-fw";
bootph-pre-ram;
ti,sci = <&sms>;
ti,sci-dev-id = <304>;
ti,sci-proc-ids = <0x80 0xff>;
/* reserved for early-stage bootloader */
status = "reserved";
};
};

2
arch/arm64/boot/dts/ti/k3-j722s-evm.dts
View File

@ -436,7 +436,7 @@ J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */
J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */
J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */
>;
};

5
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
View File

@ -429,6 +429,11 @@ &wkup_r5fss0_core0 {
firmware-name = "j722s-wkup-r5f0_0-fw";
};
/* MAIN domain overrides */
&hsm {
firmware-name = "j722s-hsm-m4f-fw";
};
&main_conf {
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";

3
arch/arm64/boot/dts/ti/k3-j722s.dtsi
View File

@ -162,7 +162,7 @@ cbass_main: bus@f0000 {
<0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
<0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
<0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */
<0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
@ -173,6 +173,7 @@ cbass_main: bus@f0000 {
<0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
<0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */

4
arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi
View File

@ -15,3 +15,7 @@ &mcu_r5fss0_core0 {
&mcu_r5fss0_core1 {
firmware-name = "j742s2-mcu-r5f0_1-fw";
};
&hsm {
firmware-name = "j742s2-hsm-m4f-fw";
};

4
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
View File

@ -509,10 +509,10 @@ J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */
J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */
J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */
J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */
J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */
J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */
J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */
J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */
J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
>;
};
};

36
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
View File

@ -2378,42 +2378,6 @@ watchdog3: watchdog@2230000 {
assigned-clock-parents = <&k3_clks 351 4>;
};
watchdog4: watchdog@2240000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2240000 0x00 0x100>;
clocks = <&k3_clks 352 0>;
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 352 0>;
assigned-clock-parents = <&k3_clks 352 4>;
};
watchdog5: watchdog@2250000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2250000 0x00 0x100>;
clocks = <&k3_clks 353 0>;
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 353 0>;
assigned-clock-parents = <&k3_clks 353 4>;
};
watchdog6: watchdog@2260000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2260000 0x00 0x100>;
clocks = <&k3_clks 354 0>;
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 354 0>;
assigned-clock-parents = <&k3_clks 354 4>;
};
watchdog7: watchdog@2270000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2270000 0x00 0x100>;
clocks = <&k3_clks 355 0>;
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 355 0>;
assigned-clock-parents = <&k3_clks 355 4>;
};
/*
* The following RTI instances are coupled with MCU R5Fs, c7x and
* GPU so keeping them reserved as these will be used by their

17
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
View File

@ -762,4 +762,21 @@ mcu_watchdog1: watchdog@40610000 {
/* reserved for MCU_R5F0_1 */
status = "reserved";
};
hsm: remoteproc@43c00000 {
compatible = "ti,hsm-m4fss";
/* contiguous regions but instantiated separately in HW */
reg = <0x00 0x43c00000 0x00 0x20000>,
<0x00 0x43c20000 0x00 0x10000>,
<0x00 0x43c30000 0x00 0x10000>;
reg-names = "sram0_0", "sram0_1", "sram1";
resets = <&k3_reset 371 1>;
firmware-name = "j784s4-hsm-m4f-fw";
bootph-pre-ram;
ti,sci = <&sms>;
ti,sci-dev-id = <371>;
ti,sci-proc-ids = <0x80 0xff>;
/* reserved for early-stage bootloader */
status = "reserved";
};
};

58
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
View File

@ -6,17 +6,40 @@
*/
&cbass_main {
c71_3: dsp@67800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x67800000 0x00 0x00080000>,
<0x00 0x67e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
resets = <&k3_reset 40 1>;
firmware-name = "j784s4-c71_3-fw";
ti,sci = <&sms>;
ti,sci-dev-id = <40>;
ti,sci-proc-ids = <0x33 0xff>;
status = "disabled";
watchdog4: watchdog@2240000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2240000 0x00 0x100>;
clocks = <&k3_clks 352 0>;
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 352 0>;
assigned-clock-parents = <&k3_clks 352 4>;
};
watchdog5: watchdog@2250000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2250000 0x00 0x100>;
clocks = <&k3_clks 353 0>;
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 353 0>;
assigned-clock-parents = <&k3_clks 353 4>;
};
watchdog6: watchdog@2260000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2260000 0x00 0x100>;
clocks = <&k3_clks 354 0>;
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 354 0>;
assigned-clock-parents = <&k3_clks 354 4>;
};
watchdog7: watchdog@2270000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2270000 0x00 0x100>;
clocks = <&k3_clks 355 0>;
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 355 0>;
assigned-clock-parents = <&k3_clks 355 4>;
};
pcie2_rc: pcie@2920000 {
@ -113,6 +136,19 @@ serdes2: serdes@5020000 {
status = "disabled";
};
};
c71_3: dsp@67800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x67800000 0x00 0x00080000>,
<0x00 0x67e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
resets = <&k3_reset 40 1>;
firmware-name = "j784s4-c71_3-fw";
ti,sci = <&sms>;
ti,sci-dev-id = <40>;
ti,sci-proc-ids = <0x33 0xff>;
status = "disabled";
};
};
&scm_conf {