diff --git a/Documentation/ABI/testing/sysfs-class-power b/Documentation/ABI/testing/sysfs-class-power index 40213c73bc9c..dbccb2fcd7ce 100644 --- a/Documentation/ABI/testing/sysfs-class-power +++ b/Documentation/ABI/testing/sysfs-class-power @@ -34,7 +34,7 @@ Description: Describes the main type of the supply. Access: Read - Valid values: "Battery", "UPS", "Mains", "USB" + Valid values: "Battery", "UPS", "Mains", "USB", "Wireless" ===== Battery Properties ===== @@ -108,7 +108,8 @@ Description: which they average readings to smooth out the reported value. Access: Read - Valid values: Represented in microamps + Valid values: Represented in microamps. Negative values are used + for discharging batteries, positive values for charging batteries. What: /sys/class/power_supply//current_max Date: October 2010 @@ -127,7 +128,8 @@ Description: This value is not averaged/smoothed. Access: Read - Valid values: Represented in microamps + Valid values: Represented in microamps. Negative values are used + for discharging batteries, positive values for charging batteries. What: /sys/class/power_supply//charge_control_limit Date: Oct 2012 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index ad1296f0bfcc..08e4fb8cc779 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5974,6 +5974,14 @@ improve timer resolution at the expense of processing more timer interrupts. + xen.event_eoi_delay= [XEN] + How long to delay EOI handling in case of event + storms (jiffies). Default is 10. + + xen.event_loop_timeout= [XEN] + After which time (jiffies) the event handling loop + should start to delay EOI handling. Default is 2. + nopv= [X86,XEN,KVM,HYPER_V,VMWARE] Disables the PV optimizations forcing the guest to run as generic guest with no PV drivers. Currently support diff --git a/Documentation/admin-guide/xfs.rst b/Documentation/admin-guide/xfs.rst index f461d6c33534..86de8a1ad91c 100644 --- a/Documentation/admin-guide/xfs.rst +++ b/Documentation/admin-guide/xfs.rst @@ -210,6 +210,28 @@ When mounting an XFS filesystem, the following options are accepted. inconsistent namespace presentation during or after a failover event. +Deprecation of V4 Format +======================== + +The V4 filesystem format lacks certain features that are supported by +the V5 format, such as metadata checksumming, strengthened metadata +verification, and the ability to store timestamps past the year 2038. +Because of this, the V4 format is deprecated. All users should upgrade +by backing up their files, reformatting, and restoring from the backup. + +Administrators and users can detect a V4 filesystem by running xfs_info +against a filesystem mountpoint and checking for a string containing +"crc=". If no such string is found, please upgrade xfsprogs to the +latest version and try again. + +The deprecation will take place in two parts. Support for mounting V4 +filesystems can now be disabled at kernel build time via Kconfig option. +The option will default to yes until September 2025, at which time it +will be changed to default to no. In September 2030, support will be +removed from the codebase entirely. + +Note: Distributors may choose to withdraw V4 format support earlier than +the dates listed above. Deprecated Mount Options ======================== @@ -217,6 +239,9 @@ Deprecated Mount Options =========================== ================ Name Removal Schedule =========================== ================ +Mounting with V4 filesystem September 2030 +ikeep/noikeep September 2025 +attr2/noattr2 September 2025 =========================== ================ @@ -331,7 +356,12 @@ The following sysctls are available for the XFS filesystem: Deprecated Sysctls ================== -None at present. +=========================== ================ + Name Removal Schedule +=========================== ================ +fs.xfs.irix_sgid_inherit September 2025 +fs.xfs.irix_symlink_mode September 2025 +=========================== ================ Removed Sysctls diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 1b4213eb3473..4d530d815484 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -1,10 +1,13 @@ Microsemi Ocelot reset controller The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the -SoC MIPS core. +SoC core. + +The reset registers are both present in the MSCC vcoreiii MIPS and +microchip Sparx5 armv8 SoC's. Required Properties: - - compatible: "mscc,ocelot-chip-reset" + - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" Example: reset@1070008 { diff --git a/Documentation/devicetree/bindings/power/reset/reboot-mode.txt b/Documentation/devicetree/bindings/power/reset/reboot-mode.txt deleted file mode 100644 index de34f27d509e..000000000000 --- a/Documentation/devicetree/bindings/power/reset/reboot-mode.txt +++ /dev/null @@ -1,25 +0,0 @@ -Generic reboot mode core map driver - -This driver get reboot mode arguments and call the write -interface to store the magic value in special register -or ram. Then the bootloader can read it and take different -action according to the argument stored. - -All mode properties are vendor specific, it is a indication to tell -the bootloader what to do when the system reboots, and should be named -as mode-xxx = (xxx is mode name, magic should be a none-zero value). - -For example modes common on Android platform: -- mode-normal: Normal reboot mode, system reboot with command "reboot". -- mode-recovery: Android Recovery mode, it is a mode to format the device or update a new image. -- mode-bootloader: Android fastboot mode, it's a mode to re-flash partitions on the Android based device. -- mode-loader: A bootloader mode, it's a mode used to download image on Rockchip platform, - usually used in development. - -Example: - reboot-mode { - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - } diff --git a/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml b/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml new file mode 100644 index 000000000000..a6c91026d4cc --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/reboot-mode.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic reboot mode core map + +maintainers: + - Andy Yan + +description: | + This driver get reboot mode arguments and call the write + interface to store the magic value in special register + or ram. Then the bootloader can read it and take different + action according to the argument stored. + + All mode properties are vendor specific, it is a indication to tell + the bootloader what to do when the system reboots, and should be named + as mode-xxx = (xxx is mode name, magic should be a non-zero value). + + For example, modes common Android platform are: + - normal: Normal reboot mode, system reboot with command "reboot". + - recovery: Android Recovery mode, it is a mode to format the device or update a new image. + - bootloader: Android fastboot mode, it's a mode to re-flash partitions on the Android based device. + - loader: A bootloader mode, it's a mode used to download image on Rockchip platform, + usually used in development. + +properties: + mode-normal: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Default value to set on a reboot if no command was provided. + +patternProperties: + "^mode-.*$": + $ref: /schemas/types.yaml#/definitions/uint32 + +examples: + - | + reboot-mode { + mode-normal = <0>; + mode-recovery = <1>; + mode-bootloader = <2>; + mode-loader = <3>; + }; +... diff --git a/Documentation/devicetree/bindings/power/supply/battery.yaml b/Documentation/devicetree/bindings/power/supply/battery.yaml index 932b736ce5c0..0c7e2e44793b 100644 --- a/Documentation/devicetree/bindings/power/supply/battery.yaml +++ b/Documentation/devicetree/bindings/power/supply/battery.yaml @@ -82,6 +82,27 @@ properties: An array containing the temperature in degree Celsius, for each of the battery capacity lookup table. + operating-range-celsius: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: operating temperature range of a battery + items: + - description: minimum temperature at which battery can operate + - description: maximum temperature at which battery can operate + + ambient-celsius: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: safe range of ambient temperature + items: + - description: alert when ambient temperature is lower than this value + - description: alert when ambient temperature is higher than this value + + alert-celsius: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: safe range of battery temperature + items: + - description: alert when battery temperature is lower than this value + - description: alert when battery temperature is higher than this value + required: - compatible @@ -130,6 +151,9 @@ examples: /* table for 10 degree Celsius */ ocv-capacity-table-2 = <4250000 100>, <4200000 95>, <4185000 90>; resistance-temp-table = <20 100>, <10 90>, <0 80>, <(-10) 60>; + operating-range-celsius = <(-30) 50>; + ambient-celsius = <(-5) 50>; + alert-celsius = <0 40>; }; charger@11 { diff --git a/Documentation/devicetree/bindings/power/supply/bq25890.txt b/Documentation/devicetree/bindings/power/supply/bq25890.txt index 3b4c69a7fa70..805040c6fff9 100644 --- a/Documentation/devicetree/bindings/power/supply/bq25890.txt +++ b/Documentation/devicetree/bindings/power/supply/bq25890.txt @@ -33,6 +33,10 @@ Optional properties: - ti,thermal-regulation-threshold: integer, temperature above which the charge current is lowered, to avoid overheating (in degrees Celsius). If omitted, the default setting will be used (120 degrees); +- ti,ibatcomp-micro-ohms: integer, value of a resistor in series with + the battery; +- ti,ibatcomp-clamp-microvolt: integer, maximum charging voltage adjustment due + to expected voltage drop on in-series resistor; Example: diff --git a/Documentation/devicetree/bindings/power/supply/bq25980.yaml b/Documentation/devicetree/bindings/power/supply/bq25980.yaml new file mode 100644 index 000000000000..f6b3dd4093ca --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/bq25980.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/supply/bq25980.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI BQ25980 Flash Charger + +maintainers: + - Dan Murphy + - Ricardo Rivera-Matos + +description: | + The BQ25980, BQ25975, and BQ25960 are a series of flash chargers intended + for use in high-power density portable electronics. These inductorless + switching chargers can provide over 97% efficiency by making use of the + switched capacitor architecture. + +allOf: + - $ref: power-supply.yaml# + +properties: + compatible: + enum: + - ti,bq25980 + - ti,bq25975 + - ti,bq25960 + + reg: + maxItems: 1 + + ti,watchdog-timeout-ms: + description: | + Watchdog timer in milli seconds. 0 disables the watchdog. + default: 0 + minimum: 0 + maximum: 300000 + enum: [ 0, 5000, 10000, 50000, 300000] + + ti,sc-ovp-limit-microvolt: + description: | + Minimum input voltage limit in micro volts with a when the charger is in + switch cap mode. 100000 micro volt step. + default: 17800000 + minimum: 14000000 + maximum: 22000000 + + ti,sc-ocp-limit-microamp: + description: | + Maximum input current limit in micro amps with a 100000 micro amp step. + minimum: 100000 + maximum: 3300000 + + ti,bypass-ovp-limit-microvolt: + description: | + Minimum input voltage limit in micro volts with a when the charger is in + switch cap mode. 50000 micro volt step. + minimum: 7000000 + maximum: 12750000 + + ti,bypass-ocp-limit-microamp: + description: | + Maximum input current limit in micro amps with a 100000 micro amp step. + minimum: 100000 + maximum: 3300000 + + ti,bypass-enable: + type: boolean + description: Enables bypass mode at boot time + + interrupts: + description: | + Indicates that the device state has changed. + + monitored-battery: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the battery node being monitored + +required: + - compatible + - reg + - monitored-battery + +unevaluatedProperties: false + +examples: + - | + bat: battery { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <4000000>; + constant-charge-voltage-max-microvolt = <8400000>; + precharge-current-microamp = <160000>; + charge-term-current-microamp = <160000>; + }; + #include + #include + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + bq25980: charger@65 { + compatible = "ti,bq25980"; + reg = <0x65>; + interrupt-parent = <&gpio1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + ti,watchdog-timer = <0>; + ti,sc-ocp-limit-microamp = <2000000>; + ti,sc-ovp-limit-microvolt = <17800000>; + monitored-battery = <&bat>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml index 82f682705f44..45beefccf31a 100644 --- a/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml @@ -51,6 +51,7 @@ properties: - ti,bq27621 - ti,bq27z561 - ti,bq28z610 + - ti,bq34z100 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/power/supply/charger-manager.txt b/Documentation/devicetree/bindings/power/supply/charger-manager.txt index ec4fe9de3137..b5ae9061b7a0 100644 --- a/Documentation/devicetree/bindings/power/supply/charger-manager.txt +++ b/Documentation/devicetree/bindings/power/supply/charger-manager.txt @@ -3,24 +3,32 @@ charger-manager bindings Required properties : - compatible : "charger-manager" - - <>-supply : for regulator consumer - - cm-num-chargers : number of chargers + - <>-supply : for regulator consumer, named according to cm-regulator-name - cm-chargers : name of chargers - cm-fuel-gauge : name of battery fuel gauge - subnode : - cm-regulator-name : name of charger regulator - subnode : - - cm-cable-name : name of charger cable + - cm-cable-name : name of charger cable - one of USB, USB-HOST, + SDP, DCP, CDP, ACA, FAST-CHARGER, SLOW-CHARGER, WPT, + PD, DOCK, JIG, or MECHANICAL - cm-cable-extcon : name of extcon dev (optional) - cm-cable-min : minimum current of cable (optional) - cm-cable-max : maximum current of cable Optional properties : - cm-name : charger manager's name (default : "battery") - - cm-poll-mode : polling mode (enum polling_modes) - - cm-poll-interval : polling interval - - cm-battery-stat : battery status (enum data_source) - - cm-fullbatt-* : data for full battery checking + - cm-poll-mode : polling mode - 0 for disabled, 1 for always, 2 for when + external power is connected, or 3 for when charging. If not present, + then polling is disabled + - cm-poll-interval : polling interval (in ms) + - cm-battery-stat : battery status - 0 for battery always present, 1 for no + battery, 2 to check presence via fuel gauge, or 3 to check presence + via charger + - cm-fullbatt-vchkdrop-volt : voltage drop (in uV) before restarting charging + - cm-fullbatt-voltage : voltage (in uV) of full battery + - cm-fullbatt-soc : state of charge to consider as full battery + - cm-fullbatt-capacity : capcity (in uAh) to consider as full battery - cm-thermal-zone : name of external thermometer's thermal zone - cm-battery-* : threshold battery temperature for charging -cold : critical cold temperature of battery for charging @@ -29,6 +37,10 @@ Optional properties : -temp-diff : temperature difference to allow recharging - cm-dis/charging-max = limits of charging duration +Deprecated properties: + - cm-num-chargers + - cm-fullbatt-vchkdrop-ms + Example : charger-manager@0 { compatible = "charger-manager"; @@ -39,13 +51,11 @@ Example : cm-poll-mode = <1>; cm-poll-interval = <30000>; - cm-fullbatt-vchkdrop-ms = <30000>; cm-fullbatt-vchkdrop-volt = <150000>; cm-fullbatt-soc = <100>; cm-battery-stat = <3>; - cm-num-chargers = <3>; cm-chargers = "charger0", "charger1", "charger2"; cm-fuel-gauge = "fuelgauge0"; @@ -71,7 +81,7 @@ Example : cm-cable-max = <500000>; }; cable@1 { - cm-cable-name = "TA"; + cm-cable-name = "SDP"; cm-cable-extcon = "extcon-dev.0"; cm-cable-min = <650000>; cm-cable-max = <675000>; diff --git a/Documentation/devicetree/bindings/power/supply/gpio-charger.yaml b/Documentation/devicetree/bindings/power/supply/gpio-charger.yaml index 6244b8ee9402..89f8e2bcb2d7 100644 --- a/Documentation/devicetree/bindings/power/supply/gpio-charger.yaml +++ b/Documentation/devicetree/bindings/power/supply/gpio-charger.yaml @@ -39,6 +39,25 @@ properties: maxItems: 1 description: GPIO indicating the charging status + charge-current-limit-gpios: + minItems: 1 + maxItems: 32 + description: GPIOs used for current limiting + + charge-current-limit-mapping: + description: List of tuples with current in uA and a GPIO bitmap (in + this order). The tuples must be provided in descending order of the + current limit. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: + Current limit in uA + - description: + Encoded GPIO setting. Bit 0 represents last GPIO from the + charge-current-limit-gpios property. Bit 1 second to last + GPIO and so on. + required: - compatible @@ -47,6 +66,12 @@ anyOf: - gpios - required: - charge-status-gpios + - required: + - charge-current-limit-gpios + +dependencies: + charge-current-limit-gpios: [ charge-current-limit-mapping ] + charge-current-limit-mapping: [ charge-current-limit-gpios ] additionalProperties: false @@ -60,4 +85,10 @@ examples: gpios = <&gpd 28 GPIO_ACTIVE_LOW>; charge-status-gpios = <&gpc 27 GPIO_ACTIVE_LOW>; + + charge-current-limit-gpios = <&gpioA 11 GPIO_ACTIVE_HIGH>, + <&gpioA 12 GPIO_ACTIVE_HIGH>; + charge-current-limit-mapping = <2500000 0x00>, // 2.5 A => both GPIOs low + <700000 0x01>, // 700 mA => GPIO A.12 high + <0 0x02>; // 0 mA => GPIO A.11 high }; diff --git a/Documentation/devicetree/bindings/power/supply/ingenic,battery.txt b/Documentation/devicetree/bindings/power/supply/ingenic,battery.txt deleted file mode 100644 index 66430bf73815..000000000000 --- a/Documentation/devicetree/bindings/power/supply/ingenic,battery.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Ingenic JZ47xx battery bindings - -Required properties: - -- compatible: Must be "ingenic,jz4740-battery". -- io-channels: phandle and IIO specifier pair to the IIO device. - Format described in iio-bindings.txt. -- monitored-battery: phandle to a "simple-battery" compatible node. - -The "monitored-battery" property must be a phandle to a node using the format -described in battery.txt, with the following properties being required: - -- voltage-min-design-microvolt: Drained battery voltage. -- voltage-max-design-microvolt: Fully charged battery voltage. - -Example: - -#include - -simple_battery: battery { - compatible = "simple-battery"; - voltage-min-design-microvolt = <3600000>; - voltage-max-design-microvolt = <4200000>; -}; - -ingenic_battery { - compatible = "ingenic,jz4740-battery"; - io-channels = <&adc INGENIC_ADC_BATTERY>; - io-channel-names = "battery"; - monitored-battery = <&simple_battery>; -}; diff --git a/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml b/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml new file mode 100644 index 000000000000..867e3e6b7e80 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019-2020 Artur Rojek +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/supply/ingenic,battery.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Ingenic JZ47xx battery bindings + +maintainers: + - Artur Rojek + +properties: + compatible: + oneOf: + - const: ingenic,jz4740-battery + - items: + - enum: + - ingenic,jz4725b-battery + - ingenic,jz4770-battery + - const: ingenic,jz4740-battery + + io-channels: + maxItems: 1 + + io-channel-names: + const: battery + + monitored-battery: + description: > + phandle to a "simple-battery" compatible node. + + This property must be a phandle to a node using the format described + in battery.yaml, with the following properties being required: + - voltage-min-design-microvolt: drained battery voltage, + - voltage-max-design-microvolt: fully charged battery voltage. + +required: + - compatible + - io-channels + - io-channel-names + - monitored-battery + +additionalProperties: false + +examples: + - | + #include + + simple_battery: battery { + compatible = "simple-battery"; + voltage-min-design-microvolt = <3600000>; + voltage-max-design-microvolt = <4200000>; + }; + + ingenic-battery { + compatible = "ingenic,jz4740-battery"; + io-channels = <&adc INGENIC_ADC_BATTERY>; + io-channel-names = "battery"; + monitored-battery = <&simple_battery>; + }; diff --git a/Documentation/devicetree/bindings/power/supply/max17040_battery.txt b/Documentation/devicetree/bindings/power/supply/max17040_battery.txt index 4e0186b8380f..c802f664b508 100644 --- a/Documentation/devicetree/bindings/power/supply/max17040_battery.txt +++ b/Documentation/devicetree/bindings/power/supply/max17040_battery.txt @@ -2,7 +2,9 @@ max17040_battery ~~~~~~~~~~~~~~~~ Required properties : - - compatible : "maxim,max17040" or "maxim,max77836-battery" + - compatible : "maxim,max17040", "maxim,max17041", "maxim,max17043", + "maxim,max17044", "maxim,max17048", "maxim,max17049", + "maxim,max17058", "maxim,max17059" or "maxim,max77836-battery" - reg: i2c slave address Optional properties : @@ -11,6 +13,15 @@ Optional properties : generated. Can be configured from 1 up to 32 (%). If skipped the power up default value of 4 (%) will be used. +- maxim,double-soc : Certain devices return double the capacity. + Specify this boolean property to divide the + reported value in 2 and thus normalize it. + SOC == State of Charge == Capacity. +- maxim,rcomp : A value to compensate readings for various + battery chemistries and operating temperatures. + max17040,41 have 2 byte rcomp, default to + 0x97 0x00. All other devices have one byte + rcomp, default to 0x97. - interrupts : Interrupt line see Documentation/devicetree/ bindings/interrupt-controller/interrupts.txt - wakeup-source : This device has wakeup capabilities. Use this @@ -31,3 +42,11 @@ Example: interrupts = <2 IRQ_TYPE_EDGE_FALLING>; wakeup-source; }; + + battery-fuel-gauge@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + maxim,rcomp = /bits/ 8 <0x56>; + maxim,alert-low-soc-level = <10>; + maxim,double-soc; + }; diff --git a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml new file mode 100644 index 000000000000..193a23af2007 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/supply/summit,smb347-charger.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Battery charger driver for SMB345, SMB347 and SMB358 + +maintainers: + - David Heidelberg + - Dmitry Osipenko + +properties: + compatible: + enum: + - summit,smb345 + - summit,smb347 + - summit,smb358 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + monitored-battery: + description: phandle to the battery node + $ref: /schemas/types.yaml#/definitions/phandle + + summit,enable-usb-charging: + type: boolean + description: Enable charging through USB. + + summit,enable-otg-charging: + type: boolean + description: Provide power for USB OTG + + summit,enable-mains-charging: + type: boolean + description: Enable charging through mains + + summit,enable-charge-control: + description: Enable charging control + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SMB3XX_CHG_ENABLE_SW SW (I2C interface) + - 1 # SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW Pin control (Active Low) + - 2 # SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH Pin control (Active High) + + summit,fast-voltage-threshold-microvolt: + description: Voltage threshold to transit to fast charge mode (in uV) + minimum: 2400000 + maximum: 3000000 + + summit,mains-current-limit-microamp: + description: Maximum input current from AC/DC input (in uA) + + summit,usb-current-limit-microamp: + description: Maximum input current from USB input (in uA) + + summit,charge-current-compensation-microamp: + description: Charge current compensation (in uA) + + summit,chip-temperature-threshold-celsius: + description: Chip temperature for thermal regulation in °C. + enum: [100, 110, 120, 130] + + summit,soft-compensation-method: + description: Soft temperature limit compensation method + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SMB3XX_SOFT_TEMP_COMPENSATE_NONE Compensation none + - 1 # SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT Current compensation + - 2 # SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE Voltage compensation + +allOf: + - if: + properties: + compatible: + enum: + - summit,smb345 + - summit,smb358 + + then: + properties: + summit,mains-current-limit-microamp: + enum: [ 300000, 500000, 700000, 1000000, + 1500000, 1800000, 2000000] + + summit,usb-current-limit-microamp: + enum: [ 300000, 500000, 700000, 1000000, + 1500000, 1800000, 2000000] + + summit,charge-current-compensation-microamp: + enum: [200000, 450000, 600000, 900000] + + else: + properties: + summit,mains-current-limit-microamp: + enum: [ 300000, 500000, 700000, 900000, 1200000, + 1500000, 1800000, 2000000, 2200000, 2500000] + + summit,usb-current-limit-microamp: + enum: [ 300000, 500000, 700000, 900000, 1200000, + 1500000, 1800000, 2000000, 2200000, 2500000] + + summit,charge-current-compensation-microamp: + enum: [250000, 700000, 900000, 1200000] + +required: + - compatible + - reg + +anyOf: + - required: + - summit,enable-usb-charging + - required: + - summit,enable-otg-charging + - required: + - summit,enable-mains-charging + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@7f { + compatible = "summit,smb347"; + reg = <0x7f>; + + summit,enable-charge-control = ; + summit,chip-temperature-threshold-celsius = <110>; + summit,mains-current-limit-microamp = <2000000>; + summit,usb-current-limit-microamp = <500000>; + summit,enable-usb-charging; + summit,enable-mains-charging; + + monitored-battery = <&battery>; + }; + }; + + battery: battery-cell { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <1800000>; + operating-range-celsius = <0 45>; + alert-celsius = <3 42>; + }; diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst index 57047dcb8d19..1f9ea8221f80 100644 --- a/Documentation/gpu/amdgpu.rst +++ b/Documentation/gpu/amdgpu.rst @@ -206,8 +206,8 @@ pp_power_profile_mode .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c :doc: pp_power_profile_mode -*_busy_percent -~~~~~~~~~~~~~~ +\*_busy_percent +~~~~~~~~~~~~~~~ .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c :doc: gpu_busy_percent diff --git a/MAINTAINERS b/MAINTAINERS index 264b07e1f67b..ddc2be1d1381 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5231,7 +5231,6 @@ F: kernel/dma/ DMA-BUF HEAPS FRAMEWORK M: Sumit Semwal -R: Andrew F. Davis R: Benjamin Gaignard R: Liam Mark R: Laura Abbott @@ -6652,13 +6651,6 @@ L: iommu@lists.linux-foundation.org S: Maintained F: drivers/iommu/exynos-iommu.c -EZchip NPS platform support -M: Vineet Gupta -M: Ofer Levi -S: Supported -F: arch/arc/boot/dts/eznps.dts -F: arch/arc/plat-eznps - F2FS FILE SYSTEM M: Jaegeuk Kim M: Chao Yu @@ -11619,6 +11611,7 @@ M: Microchip Linux Driver Support L: linux-mips@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/mips/mscc.txt +F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt F: arch/mips/boot/dts/mscc/ F: arch/mips/configs/generic/board-ocelot.config F: arch/mips/generic/board-ocelot.c @@ -17411,7 +17404,7 @@ S: Maintained F: drivers/thermal/ti-soc-thermal/ TI BQ27XXX POWER SUPPLY DRIVER -R: Andrew F. Davis +R: Dan Murphy F: drivers/power/supply/bq27xxx_battery.c F: drivers/power/supply/bq27xxx_battery_i2c.c F: include/linux/power/bq27xxx_battery.h diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index ba00c4e1e1c2..19f8f2367d6d 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -96,8 +96,6 @@ menu "ARC Platform/SoC/Board" source "arch/arc/plat-tb10x/Kconfig" source "arch/arc/plat-axs10x/Kconfig" -#New platform adds here -source "arch/arc/plat-eznps/Kconfig" source "arch/arc/plat-hsdk/Kconfig" endmenu diff --git a/arch/arc/Makefile b/arch/arc/Makefile index d00f8b8afd08..0c6bf0d1df7a 100644 --- a/arch/arc/Makefile +++ b/arch/arc/Makefile @@ -94,13 +94,8 @@ core-y += arch/arc/boot/dts/ core-y += arch/arc/plat-sim/ core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/ core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/ -core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/ core-$(CONFIG_ARC_SOC_HSDK) += arch/arc/plat-hsdk/ -ifdef CONFIG_ARC_PLAT_EZNPS -KBUILD_CPPFLAGS += -I$(srctree)/arch/arc/plat-eznps/include -endif - drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/ libs-y += arch/arc/lib/ $(LIBGCC) diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi index 79ec27c043c1..2a151607b080 100644 --- a/arch/arc/boot/dts/axc001.dtsi +++ b/arch/arc/boot/dts/axc001.dtsi @@ -91,7 +91,7 @@ arcpct0: pct { * avoid duplicating the MB dtsi file given that IRQ from * this intc to cpu intc are different for axs101 and axs103 */ - mb_intc: dw-apb-ictl@e0012000 { + mb_intc: interrupt-controller@e0012000 { #interrupt-cells = <1>; compatible = "snps,dw-apb-ictl"; reg = < 0x0 0xe0012000 0x0 0x200 >; diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi index ac8e1b463a70..cd1edcf4f95e 100644 --- a/arch/arc/boot/dts/axc003.dtsi +++ b/arch/arc/boot/dts/axc003.dtsi @@ -129,7 +129,7 @@ mmc@15000 { * avoid duplicating the MB dtsi file given that IRQ from * this intc to cpu intc are different for axs101 and axs103 */ - mb_intc: dw-apb-ictl@e0012000 { + mb_intc: interrupt-controller@e0012000 { #interrupt-cells = <1>; compatible = "snps,dw-apb-ictl"; reg = < 0x0 0xe0012000 0x0 0x200 >; diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi index 9da21e7fd246..70779386ca79 100644 --- a/arch/arc/boot/dts/axc003_idu.dtsi +++ b/arch/arc/boot/dts/axc003_idu.dtsi @@ -135,7 +135,7 @@ mmc@15000 { * avoid duplicating the MB dtsi file given that IRQ from * this intc to cpu intc are different for axs101 and axs103 */ - mb_intc: dw-apb-ictl@e0012000 { + mb_intc: interrupt-controller@e0012000 { #interrupt-cells = <1>; compatible = "snps,dw-apb-ictl"; reg = < 0x0 0xe0012000 0x0 0x200 >; diff --git a/arch/arc/boot/dts/eznps.dts b/arch/arc/boot/dts/eznps.dts deleted file mode 100644 index a7e2e8d8ff06..000000000000 --- a/arch/arc/boot/dts/eznps.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright(c) 2015 EZchip Technologies. - */ - -/dts-v1/; - -/ { - compatible = "ezchip,arc-nps"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - present-cpus = "0-1,16-17"; - possible-cpus = "0-4095"; - - aliases { - ethernet0 = &gmac0; - }; - - chosen { - bootargs = "earlycon=uart8250,mmio32be,0xf7209000,115200n8 console=ttyS0,115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512M */ - }; - - clocks { - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <83333333>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - /* child and parent address space 1:1 mapped */ - ranges; - - intc: interrupt-controller { - compatible = "ezchip,nps400-ic"; - interrupt-controller; - #interrupt-cells = <1>; - }; - - timer0: timer_clkevt { - compatible = "snps,arc-timer"; - interrupts = <3>; - clocks = <&sysclk>; - }; - - timer1: timer_clksrc { - compatible = "ezchip,nps400-timer"; - clocks = <&sysclk>; - clock-names="sysclk"; - }; - - uart@f7209000 { - compatible = "snps,dw-apb-uart"; - device_type = "serial"; - reg = <0xf7209000 0x100>; - interrupts = <6>; - clocks = <&sysclk>; - clock-names="baudclk"; - baud = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - native-endian; - }; - - gmac0: ethernet@f7470000 { - compatible = "ezchip,nps-mgt-enet"; - reg = <0xf7470000 0x1940>; - interrupts = <7>; - /* Filled in by U-Boot */ - mac-address = [ 00 C0 00 F0 04 03 ]; - }; - }; -}; diff --git a/arch/arc/boot/dts/vdk_axc003.dtsi b/arch/arc/boot/dts/vdk_axc003.dtsi index f8be7ba8dad4..c21d0eb07bf6 100644 --- a/arch/arc/boot/dts/vdk_axc003.dtsi +++ b/arch/arc/boot/dts/vdk_axc003.dtsi @@ -46,7 +46,7 @@ debug_uart: dw-apb-uart@5000 { }; - mb_intc: dw-apb-ictl@e0012000 { + mb_intc: interrupt-controller@e0012000 { #interrupt-cells = <1>; compatible = "snps,dw-apb-ictl"; reg = < 0xe0012000 0x200 >; diff --git a/arch/arc/boot/dts/vdk_axc003_idu.dtsi b/arch/arc/boot/dts/vdk_axc003_idu.dtsi index 0afa3e53a4e3..4d348853ac7c 100644 --- a/arch/arc/boot/dts/vdk_axc003_idu.dtsi +++ b/arch/arc/boot/dts/vdk_axc003_idu.dtsi @@ -54,7 +54,7 @@ debug_uart: dw-apb-uart@5000 { }; - mb_intc: dw-apb-ictl@e0012000 { + mb_intc: interrupt-controller@e0012000 { #interrupt-cells = <1>; compatible = "snps,dw-apb-ictl"; reg = < 0xe0012000 0x200 >; diff --git a/arch/arc/configs/nps_defconfig b/arch/arc/configs/nps_defconfig deleted file mode 100644 index f7a978dfdf1d..000000000000 --- a/arch/arc/configs/nps_defconfig +++ /dev/null @@ -1,80 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y -# CONFIG_EPOLL is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_EMBEDDED=y -CONFIG_PERF_EVENTS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_ISA_ARCOMPACT=y -CONFIG_KPROBES=y -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARC_PLAT_EZNPS=y -CONFIG_SMP=y -CONFIG_NR_CPUS=4096 -CONFIG_ARC_CACHE_LINE_SHIFT=5 -# CONFIG_ARC_CACHE_PAGES is not set -# CONFIG_ARC_HAS_LLSC is not set -CONFIG_ARC_KVADDR_SIZE=402 -CONFIG_ARC_EMUL_UNALIGNED=y -CONFIG_PREEMPT=y -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=1 -CONFIG_BLK_DEV_RAM_SIZE=2048 -CONFIG_NETDEVICES=y -CONFIG_NETCONSOLE=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_PROC_KCORE=y -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_ROOT_NFS=y -CONFIG_DEBUG_INFO=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_ENABLE_DEFAULT_TRACERS=y diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h index c614857eb209..5afc79c9b2f5 100644 --- a/arch/arc/include/asm/atomic.h +++ b/arch/arc/include/asm/atomic.h @@ -14,8 +14,6 @@ #include #include -#ifndef CONFIG_ARC_PLAT_EZNPS - #define atomic_read(v) READ_ONCE((v)->counter) #ifdef CONFIG_ARC_HAS_LLSC @@ -45,7 +43,7 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \ \ /* \ * Explicit full memory barrier needed before/after as \ - * LLOCK/SCOND thmeselves don't provide any such semantics \ + * LLOCK/SCOND themselves don't provide any such semantics \ */ \ smp_mb(); \ \ @@ -71,7 +69,7 @@ static inline int atomic_fetch_##op(int i, atomic_t *v) \ \ /* \ * Explicit full memory barrier needed before/after as \ - * LLOCK/SCOND thmeselves don't provide any such semantics \ + * LLOCK/SCOND themselves don't provide any such semantics \ */ \ smp_mb(); \ \ @@ -195,108 +193,6 @@ ATOMIC_OPS(andnot, &= ~, bic) ATOMIC_OPS(or, |=, or) ATOMIC_OPS(xor, ^=, xor) -#else /* CONFIG_ARC_PLAT_EZNPS */ - -static inline int atomic_read(const atomic_t *v) -{ - int temp; - - __asm__ __volatile__( - " ld.di %0, [%1]" - : "=r"(temp) - : "r"(&v->counter) - : "memory"); - return temp; -} - -static inline void atomic_set(atomic_t *v, int i) -{ - __asm__ __volatile__( - " st.di %0,[%1]" - : - : "r"(i), "r"(&v->counter) - : "memory"); -} - -#define ATOMIC_OP(op, c_op, asm_op) \ -static inline void atomic_##op(int i, atomic_t *v) \ -{ \ - __asm__ __volatile__( \ - " mov r2, %0\n" \ - " mov r3, %1\n" \ - " .word %2\n" \ - : \ - : "r"(i), "r"(&v->counter), "i"(asm_op) \ - : "r2", "r3", "memory"); \ -} \ - -#define ATOMIC_OP_RETURN(op, c_op, asm_op) \ -static inline int atomic_##op##_return(int i, atomic_t *v) \ -{ \ - unsigned int temp = i; \ - \ - /* Explicit full memory barrier needed before/after */ \ - smp_mb(); \ - \ - __asm__ __volatile__( \ - " mov r2, %0\n" \ - " mov r3, %1\n" \ - " .word %2\n" \ - " mov %0, r2" \ - : "+r"(temp) \ - : "r"(&v->counter), "i"(asm_op) \ - : "r2", "r3", "memory"); \ - \ - smp_mb(); \ - \ - temp c_op i; \ - \ - return temp; \ -} - -#define ATOMIC_FETCH_OP(op, c_op, asm_op) \ -static inline int atomic_fetch_##op(int i, atomic_t *v) \ -{ \ - unsigned int temp = i; \ - \ - /* Explicit full memory barrier needed before/after */ \ - smp_mb(); \ - \ - __asm__ __volatile__( \ - " mov r2, %0\n" \ - " mov r3, %1\n" \ - " .word %2\n" \ - " mov %0, r2" \ - : "+r"(temp) \ - : "r"(&v->counter), "i"(asm_op) \ - : "r2", "r3", "memory"); \ - \ - smp_mb(); \ - \ - return temp; \ -} - -#define ATOMIC_OPS(op, c_op, asm_op) \ - ATOMIC_OP(op, c_op, asm_op) \ - ATOMIC_OP_RETURN(op, c_op, asm_op) \ - ATOMIC_FETCH_OP(op, c_op, asm_op) - -ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3) -#define atomic_sub(i, v) atomic_add(-(i), (v)) -#define atomic_sub_return(i, v) atomic_add_return(-(i), (v)) -#define atomic_fetch_sub(i, v) atomic_fetch_add(-(i), (v)) - -#undef ATOMIC_OPS -#define ATOMIC_OPS(op, c_op, asm_op) \ - ATOMIC_OP(op, c_op, asm_op) \ - ATOMIC_FETCH_OP(op, c_op, asm_op) - -ATOMIC_OPS(and, &=, CTOP_INST_AAND_DI_R2_R2_R3) -ATOMIC_OPS(or, |=, CTOP_INST_AOR_DI_R2_R2_R3) -ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3) - -#endif /* CONFIG_ARC_PLAT_EZNPS */ - #undef ATOMIC_OPS #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN diff --git a/arch/arc/include/asm/barrier.h b/arch/arc/include/asm/barrier.h index 7823811e7cf5..4637de9e02fa 100644 --- a/arch/arc/include/asm/barrier.h +++ b/arch/arc/include/asm/barrier.h @@ -27,7 +27,7 @@ #define rmb() asm volatile("dmb 1\n" : : : "memory") #define wmb() asm volatile("dmb 2\n" : : : "memory") -#elif !defined(CONFIG_ARC_PLAT_EZNPS) /* CONFIG_ISA_ARCOMPACT */ +#else /* * ARCompact based cores (ARC700) only have SYNC instruction which is super @@ -37,13 +37,6 @@ #define mb() asm volatile("sync\n" : : : "memory") -#else /* CONFIG_ARC_PLAT_EZNPS */ - -#include - -#define mb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory") -#define rmb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RD) : "memory") - #endif #include diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h index 50eb3f64a77c..c6606f4d20d6 100644 --- a/arch/arc/include/asm/bitops.h +++ b/arch/arc/include/asm/bitops.h @@ -85,7 +85,7 @@ static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long * return (old & (1 << nr)) != 0; \ } -#elif !defined(CONFIG_ARC_PLAT_EZNPS) +#else /* !CONFIG_ARC_HAS_LLSC */ /* * Non hardware assisted Atomic-R-M-W @@ -136,55 +136,7 @@ static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long * return (old & (1UL << (nr & 0x1f))) != 0; \ } -#else /* CONFIG_ARC_PLAT_EZNPS */ - -#define BIT_OP(op, c_op, asm_op) \ -static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\ -{ \ - m += nr >> 5; \ - \ - nr = (1UL << (nr & 0x1f)); \ - if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3) \ - nr = ~nr; \ - \ - __asm__ __volatile__( \ - " mov r2, %0\n" \ - " mov r3, %1\n" \ - " .word %2\n" \ - : \ - : "r"(nr), "r"(m), "i"(asm_op) \ - : "r2", "r3", "memory"); \ -} - -#define TEST_N_BIT_OP(op, c_op, asm_op) \ -static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\ -{ \ - unsigned long old; \ - \ - m += nr >> 5; \ - \ - nr = old = (1UL << (nr & 0x1f)); \ - if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3) \ - old = ~old; \ - \ - /* Explicit full memory barrier needed before/after */ \ - smp_mb(); \ - \ - __asm__ __volatile__( \ - " mov r2, %0\n" \ - " mov r3, %1\n" \ - " .word %2\n" \ - " mov %0, r2" \ - : "+r"(old) \ - : "r"(m), "i"(asm_op) \ - : "r2", "r3", "memory"); \ - \ - smp_mb(); \ - \ - return (old & nr) != 0; \ -} - -#endif /* CONFIG_ARC_PLAT_EZNPS */ +#endif /*************************************** * Non atomic variants @@ -226,15 +178,9 @@ static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long /* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\ __TEST_N_BIT_OP(op, c_op, asm_op) -#ifndef CONFIG_ARC_PLAT_EZNPS BIT_OPS(set, |, bset) BIT_OPS(clear, & ~, bclr) BIT_OPS(change, ^, bxor) -#else -BIT_OPS(set, |, CTOP_INST_AOR_DI_R2_R2_R3) -BIT_OPS(clear, & ~, CTOP_INST_AAND_DI_R2_R2_R3) -BIT_OPS(change, ^, CTOP_INST_AXOR_DI_R2_R2_R3) -#endif /* * This routine doesn't need to be atomic. diff --git a/arch/arc/include/asm/cmpxchg.h b/arch/arc/include/asm/cmpxchg.h index c11398160240..9b87e162e539 100644 --- a/arch/arc/include/asm/cmpxchg.h +++ b/arch/arc/include/asm/cmpxchg.h @@ -20,7 +20,7 @@ __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) /* * Explicit full memory barrier needed before/after as - * LLOCK/SCOND thmeselves don't provide any such semantics + * LLOCK/SCOND themselves don't provide any such semantics */ smp_mb(); @@ -41,7 +41,7 @@ __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) return prev; } -#elif !defined(CONFIG_ARC_PLAT_EZNPS) +#else /* !CONFIG_ARC_HAS_LLSC */ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) @@ -61,33 +61,7 @@ __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) return prev; } -#else /* CONFIG_ARC_PLAT_EZNPS */ - -static inline unsigned long -__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) -{ - /* - * Explicit full memory barrier needed before/after - */ - smp_mb(); - - write_aux_reg(CTOP_AUX_GPA1, expected); - - __asm__ __volatile__( - " mov r2, %0\n" - " mov r3, %1\n" - " .word %2\n" - " mov %0, r2" - : "+r"(new) - : "r"(ptr), "i"(CTOP_INST_EXC_DI_R2_R2_R3) - : "r2", "r3", "memory"); - - smp_mb(); - - return new; -} - -#endif /* CONFIG_ARC_HAS_LLSC */ +#endif #define cmpxchg(ptr, o, n) ({ \ (typeof(*(ptr)))__cmpxchg((ptr), \ @@ -104,8 +78,6 @@ __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) -#ifndef CONFIG_ARC_PLAT_EZNPS - /* * xchg (reg with memory) based on "Native atomic" EX insn */ @@ -168,44 +140,6 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, #endif -#else /* CONFIG_ARC_PLAT_EZNPS */ - -static inline unsigned long __xchg(unsigned long val, volatile void *ptr, - int size) -{ - extern unsigned long __xchg_bad_pointer(void); - - switch (size) { - case 4: - /* - * Explicit full memory barrier needed before/after - */ - smp_mb(); - - __asm__ __volatile__( - " mov r2, %0\n" - " mov r3, %1\n" - " .word %2\n" - " mov %0, r2\n" - : "+r"(val) - : "r"(ptr), "i"(CTOP_INST_XEX_DI_R2_R2_R3) - : "r2", "r3", "memory"); - - smp_mb(); - - return val; - } - return __xchg_bad_pointer(); -} - -#define xchg(ptr, with) ({ \ - (typeof(*(ptr)))__xchg((unsigned long)(with), \ - (ptr), \ - sizeof(*(ptr))); \ -}) - -#endif /* CONFIG_ARC_PLAT_EZNPS */ - /* * "atomic" variant of xchg() * REQ: It needs to follow the same serialization rules as other atomic_xxx() diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h index c3aa775878dc..6dbf5cecc8cc 100644 --- a/arch/arc/include/asm/entry-compact.h +++ b/arch/arc/include/asm/entry-compact.h @@ -33,10 +33,6 @@ #include #include /* For THREAD_SIZE */ -#ifdef CONFIG_ARC_PLAT_EZNPS -#include -#endif - /*-------------------------------------------------------------- * Switch to Kernel Mode stack if SP points to User Mode stack * @@ -189,12 +185,6 @@ PUSHAX lp_start PUSHAX erbta -#ifdef CONFIG_ARC_PLAT_EZNPS - .word CTOP_INST_SCHD_RW - PUSHAX CTOP_AUX_GPA1 - PUSHAX CTOP_AUX_EFLAGS -#endif - lr r10, [ecr] st r10, [sp, PT_event] /* EV_Trap expects r10 to have ECR */ .endm @@ -211,11 +201,6 @@ * by hardware and that is not good. *-------------------------------------------------------------*/ .macro EXCEPTION_EPILOGUE -#ifdef CONFIG_ARC_PLAT_EZNPS - .word CTOP_INST_SCHD_RW - POPAX CTOP_AUX_EFLAGS - POPAX CTOP_AUX_GPA1 -#endif POPAX erbta POPAX lp_start @@ -278,11 +263,6 @@ PUSHAX lp_start PUSHAX bta_l\LVL\() -#ifdef CONFIG_ARC_PLAT_EZNPS - .word CTOP_INST_SCHD_RW - PUSHAX CTOP_AUX_GPA1 - PUSHAX CTOP_AUX_EFLAGS -#endif .endm /*-------------------------------------------------------------- @@ -295,11 +275,6 @@ * by hardware and that is not good. *-------------------------------------------------------------*/ .macro INTERRUPT_EPILOGUE LVL -#ifdef CONFIG_ARC_PLAT_EZNPS - .word CTOP_INST_SCHD_RW - POPAX CTOP_AUX_EFLAGS - POPAX CTOP_AUX_GPA1 -#endif POPAX bta_l\LVL\() POPAX lp_start @@ -327,13 +302,11 @@ bic \reg, sp, (THREAD_SIZE - 1) .endm -#ifndef CONFIG_ARC_PLAT_EZNPS /* Get CPU-ID of this core */ .macro GET_CPU_ID reg lr \reg, [identity] lsr \reg, \reg, 8 bmsk \reg, \reg, 7 .endm -#endif #endif /* __ASM_ARC_ENTRY_COMPACT_H */ diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h index 0fcea5bad343..e4031ecd3c8c 100644 --- a/arch/arc/include/asm/processor.h +++ b/arch/arc/include/asm/processor.h @@ -17,13 +17,6 @@ #include #include -#ifdef CONFIG_ARC_PLAT_EZNPS -struct eznps_dp { - unsigned int eflags; - unsigned int gpa1; -}; -#endif - /* Arch specific stuff which needs to be saved per task. * However these items are not so important so as to earn a place in * struct thread_info @@ -38,9 +31,6 @@ struct thread_struct { #ifdef CONFIG_ARC_FPU_SAVE_RESTORE struct arc_fpu fpu; #endif -#ifdef CONFIG_ARC_PLAT_EZNPS - struct eznps_dp dp; -#endif }; #define INIT_THREAD { \ @@ -60,17 +50,8 @@ struct task_struct; * A lot of busy-wait loops in SMP are based off of non-volatile data otherwise * get optimised away by gcc */ -#ifndef CONFIG_EZNPS_MTM_EXT - #define cpu_relax() barrier() -#else - -#define cpu_relax() \ - __asm__ __volatile__ (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory") - -#endif - #define KSTK_EIP(tsk) (task_pt_regs(tsk)->ret) #define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp) @@ -118,25 +99,7 @@ extern unsigned int get_wchan(struct task_struct *p); #define USER_KERNEL_GUTTER (VMALLOC_START - TASK_SIZE) -#ifdef CONFIG_ARC_PLAT_EZNPS -/* NPS architecture defines special window of 129M in user address space for - * special memory areas, when accessing this window the MMU do not use TLB. - * Instead MMU direct the access to: - * 0x57f00000:0x57ffffff -- 1M of closely coupled memory (aka CMEM) - * 0x58000000:0x5fffffff -- 16 huge pages, 8M each, with fixed map (aka FMTs) - * - * CMEM - is the fastest memory we got and its size is 16K. - * FMT - is used to map either to internal/external memory. - * Internal memory is the second fast memory and its size is 16M - * External memory is the biggest memory (16G) and also the slowest. - * - * STACK_TOP need to be PMD align (21bit) that is why we supply 0x57e00000. - */ -#define STACK_TOP 0x57e00000 -#else #define STACK_TOP TASK_SIZE -#endif - #define STACK_TOP_MAX STACK_TOP /* This decides where the kernel will search for a free chunk of vm diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h index 2fdb87addadc..4c3c9be5bd16 100644 --- a/arch/arc/include/asm/ptrace.h +++ b/arch/arc/include/asm/ptrace.h @@ -16,11 +16,6 @@ #ifdef CONFIG_ISA_ARCOMPACT struct pt_regs { -#ifdef CONFIG_ARC_PLAT_EZNPS - unsigned long eflags; /* Extended FLAGS */ - unsigned long gpa1; /* General Purpose Aux */ -#endif - /* Real registers */ unsigned long bta; /* bta_l1, bta_l2, erbta */ diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h index 61a97fe70b86..01f85478170d 100644 --- a/arch/arc/include/asm/setup.h +++ b/arch/arc/include/asm/setup.h @@ -9,11 +9,7 @@ #include #include -#ifdef CONFIG_ARC_PLAT_EZNPS -#define COMMAND_LINE_SIZE 2048 -#else #define COMMAND_LINE_SIZE 256 -#endif /* * Data structure to map a ID to string diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h index 94bbed88e3fc..192871608925 100644 --- a/arch/arc/include/asm/spinlock.h +++ b/arch/arc/include/asm/spinlock.h @@ -232,15 +232,9 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) __asm__ __volatile__( "1: ex %0, [%1] \n" -#ifdef CONFIG_EZNPS_MTM_EXT - " .word %3 \n" -#endif " breq %0, %2, 1b \n" : "+&r" (val) : "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__) -#ifdef CONFIG_EZNPS_MTM_EXT - , "i"(CTOP_INST_SCHD_RW) -#endif : "memory"); smp_mb(); diff --git a/arch/arc/include/asm/switch_to.h b/arch/arc/include/asm/switch_to.h index 4a3d67989d19..1f85de8288b1 100644 --- a/arch/arc/include/asm/switch_to.h +++ b/arch/arc/include/asm/switch_to.h @@ -12,19 +12,10 @@ #include #include -#ifdef CONFIG_ARC_PLAT_EZNPS -extern void dp_save_restore(struct task_struct *p, struct task_struct *n); -#define ARC_EZNPS_DP_PREV(p, n) dp_save_restore(p, n) -#else -#define ARC_EZNPS_DP_PREV(p, n) - -#endif /* !CONFIG_ARC_PLAT_EZNPS */ - struct task_struct *__switch_to(struct task_struct *p, struct task_struct *n); #define switch_to(prev, next, last) \ do { \ - ARC_EZNPS_DP_PREV(prev, next); \ dsp_save_restore(prev, next); \ fpu_save_restore(prev, next); \ last = __switch_to(prev, next);\ diff --git a/arch/arc/kernel/ctx_sw.c b/arch/arc/kernel/ctx_sw.c index e172c3333a84..1a76f2d6f694 100644 --- a/arch/arc/kernel/ctx_sw.c +++ b/arch/arc/kernel/ctx_sw.c @@ -14,9 +14,6 @@ #include #include #include -#ifdef CONFIG_ARC_PLAT_EZNPS -#include -#endif #define KSP_WORD_OFF ((TASK_THREAD + THREAD_KSP) / 4) @@ -67,17 +64,10 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task) */ #ifndef CONFIG_SMP "st %2, [@_current_task] \n\t" -#else -#ifdef CONFIG_ARC_PLAT_EZNPS - "lr r24, [%4] \n\t" -#ifndef CONFIG_EZNPS_MTM_EXT - "lsr r24, r24, 4 \n\t" -#endif #else "lr r24, [identity] \n\t" "lsr r24, r24, 8 \n\t" "bmsk r24, r24, 7 \n\t" -#endif "add2 r24, @_current_task, r24 \n\t" "st %2, [r24] \n\t" #endif @@ -115,9 +105,6 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task) : "=r"(tmp) : "n"(KSP_WORD_OFF), "r"(next), "r"(prev) -#ifdef CONFIG_ARC_PLAT_EZNPS - , "i"(CTOP_AUX_LOGIC_GLOBAL_ID) -#endif : "blink" ); diff --git a/arch/arc/kernel/devtree.c b/arch/arc/kernel/devtree.c index fa86d13df5ed..721d465f1580 100644 --- a/arch/arc/kernel/devtree.c +++ b/arch/arc/kernel/devtree.c @@ -29,8 +29,6 @@ static void __init arc_set_early_base_baud(unsigned long dt_root) else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp") || of_flat_dt_is_compatible(dt_root, "snps,hsdk")) arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x & HSDK) */ - else if (of_flat_dt_is_compatible(dt_root, "ezchip,arc-nps")) - arc_base_baud = 800000000; /* Fixed 800MHz clk (NPS) */ else arc_base_baud = 50000000; /* Fixed default 50MHz */ } diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c index efeba1fe7252..37f724ad5e39 100644 --- a/arch/arc/kernel/process.c +++ b/arch/arc/kernel/process.c @@ -116,17 +116,6 @@ void arch_cpu_idle(void) :"I"(arg)); /* can't be "r" has to be embedded const */ } -#elif defined(CONFIG_EZNPS_MTM_EXT) /* ARC700 variant in NPS */ - -void arch_cpu_idle(void) -{ - /* only the calling HW thread needs to sleep */ - __asm__ __volatile__( - ".word %0 \n" - : - :"i"(CTOP_INST_HWSCHD_WFT_IE12)); -} - #else /* ARC700 */ void arch_cpu_idle(void) @@ -278,10 +267,6 @@ void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long usp) */ regs->status32 = STATUS_U_MASK | STATUS_L_MASK | ISA_INIT_STATUS_BITS; -#ifdef CONFIG_EZNPS_MTM_EXT - regs->eflags = 0; -#endif - fpu_init_task(regs); /* bogus seed values for debugging */ diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c index eca35e02ce06..52906d314537 100644 --- a/arch/arc/kernel/smp.c +++ b/arch/arc/kernel/smp.c @@ -226,7 +226,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) } if (!cpu_online(cpu)) { - pr_info("Timeout: CPU%u FAILED to comeup !!!\n", cpu); + pr_info("Timeout: CPU%u FAILED to come up !!!\n", cpu); return -1; } diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 31f54bdd95f2..062fae46c3f8 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -281,13 +281,6 @@ ex_saved_reg1: .macro COMMIT_ENTRY_TO_MMU #if (CONFIG_ARC_MMU_VER < 4) -#ifdef CONFIG_EZNPS_MTM_EXT - /* verify if entry for this vaddr+ASID already exists */ - sr TLBProbe, [ARC_REG_TLBCOMMAND] - lr r0, [ARC_REG_TLBINDEX] - bbit0 r0, 31, 88f -#endif - /* Get free TLB slot: Set = computed from vaddr, way = random */ sr TLBGetIndex, [ARC_REG_TLBCOMMAND] diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig deleted file mode 100644 index a645bca5899a..000000000000 --- a/arch/arc/plat-eznps/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.rst. -# - -menuconfig ARC_PLAT_EZNPS - bool "\"EZchip\" ARC dev platform" - depends on ISA_ARCOMPACT - select CPU_BIG_ENDIAN - select CLKSRC_NPS if !PHYS_ADDR_T_64BIT - select EZNPS_GIC - select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET - help - Support for EZchip development platforms, - based on ARC700 cores. - We handle few flavors: - - Hardware Emulator AKA HE which is FPGA based chassis - - Simulator based on MetaWare nSIM - - NPS400 chip based on ASIC - -config EZNPS_MTM_EXT - bool "ARC-EZchip MTM Extensions" - select CPUMASK_OFFSTACK - depends on ARC_PLAT_EZNPS && SMP - default y - help - Here we add new hierarchy for CPUs topology. - We got: - Core - Thread - At the new thread level each CPU represent one HW thread. - At highest hierarchy each core contain 16 threads, - any of them seem like CPU from Linux point of view. - All threads within same core share the execution unit of the - core and HW scheduler round robin between them. - -config EZNPS_MEM_ERROR_ALIGN - bool "ARC-EZchip Memory error as an exception" - depends on EZNPS_MTM_EXT - default n - help - On the real chip of the NPS, user memory errors are handled - as a machine check exception, which is fatal, whereas on - simulator platform for NPS, is handled as a Level 2 interrupt - (just a stock ARC700) which is recoverable. This option makes - simulator behave like hardware. - -config EZNPS_SHARED_AUX_REGS - bool "ARC-EZchip Shared Auxiliary Registers Per Core" - depends on ARC_PLAT_EZNPS - default y - help - On the real chip of the NPS, auxiliary registers are shared between - all the cpus of the core, whereas on simulator platform for NPS, - each cpu has a different set of auxiliary registers. Configuration - should be unset if auxiliary registers are not shared between the cpus - of the core, so there will be a need to initialize them per cpu. diff --git a/arch/arc/plat-eznps/Makefile b/arch/arc/plat-eznps/Makefile deleted file mode 100644 index ebb9723002cf..000000000000 --- a/arch/arc/plat-eznps/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for the linux kernel. -# - -obj-y := entry.o platform.o ctop.o -obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_EZNPS_MTM_EXT) += mtm.o diff --git a/arch/arc/plat-eznps/ctop.c b/arch/arc/plat-eznps/ctop.c deleted file mode 100644 index b398e6e838a9..000000000000 --- a/arch/arc/plat-eznps/ctop.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright(c) 2015 EZchip Technologies. - */ - -#include -#include -#include - -void dp_save_restore(struct task_struct *prev, struct task_struct *next) -{ - struct eznps_dp *prev_task_dp = &prev->thread.dp; - struct eznps_dp *next_task_dp = &next->thread.dp; - - /* Here we save all Data Plane related auxiliary registers */ - prev_task_dp->eflags = read_aux_reg(CTOP_AUX_EFLAGS); - write_aux_reg(CTOP_AUX_EFLAGS, next_task_dp->eflags); - - prev_task_dp->gpa1 = read_aux_reg(CTOP_AUX_GPA1); - write_aux_reg(CTOP_AUX_GPA1, next_task_dp->gpa1); -} diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S deleted file mode 100644 index 3f18c0108e72..000000000000 --- a/arch/arc/plat-eznps/entry.S +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/******************************************************************************* - - EZNPS CPU startup Code - Copyright(c) 2012 EZchip Technologies. - - -*******************************************************************************/ -#include -#include -#include -#include - - .cpu A7 - - .section .init.text, "ax",@progbits - .align 1024 ; HW requierment for restart first PC - -ENTRY(res_service) -#if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS) - ; There is no work for HW thread id != 0 - lr r3, [CTOP_AUX_THREAD_ID] - cmp r3, 0 - jne stext -#endif - -#ifdef CONFIG_ARC_HAS_DCACHE - ; With no cache coherency mechanism D$ need to be used very carefully. - ; Address space: - ; 0G-2G: We disable CONFIG_ARC_CACHE_PAGES. - ; 2G-3G: We disable D$ by setting this bit. - ; 3G-4G: D$ is disabled by architecture. - ; FMT are huge pages for user application reside at 0-2G. - ; Only FMT left as one who can use D$ where each such page got - ; disable/enable bit for cachability. - ; Programmer will use FMT pages for private data so cache coherency - ; would not be a problem. - ; First thing we invalidate D$ - sr 1, [ARC_REG_DC_IVDC] - sr HW_COMPLY_KRN_NOT_D_CACHED, [CTOP_AUX_HW_COMPLY] -#endif - -#ifdef CONFIG_SMP - ; We set logical cpuid to be used by GET_CPUID - ; We do not use physical cpuid since we want ids to be continious when - ; it comes to cpus on the same quad cluster. - ; This is useful for applications that used shared resources of a quad - ; cluster such SRAMS. - lr r3, [CTOP_AUX_CORE_ID] - sr r3, [CTOP_AUX_LOGIC_CORE_ID] - lr r3, [CTOP_AUX_CLUSTER_ID] - ; Set logical is acheived by swap of 2 middle bits of cluster id (4 bit) - ; r3 is used since we use short instruction and we need q-class reg - .short CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST - .word CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM - sr r3, [CTOP_AUX_LOGIC_CLUSTER_ID] -#endif - - j stext -END(res_service) diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h deleted file mode 100644 index 77712c5ffe84..000000000000 --- a/arch/arc/plat-eznps/include/plat/ctop.h +++ /dev/null @@ -1,208 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright(c) 2015 EZchip Technologies. - */ - -#ifndef _PLAT_EZNPS_CTOP_H -#define _PLAT_EZNPS_CTOP_H - -#ifndef CONFIG_ARC_PLAT_EZNPS -#error "Incorrect ctop.h include" -#endif - -#include -#include -#include - -/* core auxiliary registers */ -#ifdef __ASSEMBLY__ -#define CTOP_AUX_BASE (-0x800) -#else -#define CTOP_AUX_BASE 0xFFFFF800 -#endif - -#define CTOP_AUX_GLOBAL_ID (CTOP_AUX_BASE + 0x000) -#define CTOP_AUX_CLUSTER_ID (CTOP_AUX_BASE + 0x004) -#define CTOP_AUX_CORE_ID (CTOP_AUX_BASE + 0x008) -#define CTOP_AUX_THREAD_ID (CTOP_AUX_BASE + 0x00C) -#define CTOP_AUX_LOGIC_GLOBAL_ID (CTOP_AUX_BASE + 0x010) -#define CTOP_AUX_LOGIC_CLUSTER_ID (CTOP_AUX_BASE + 0x014) -#define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018) -#define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020) -#define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024) -#define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C) -#define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030) -#define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080) -#define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C) -#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300) - -/* EZchip core instructions */ -#define CTOP_INST_HWSCHD_WFT_IE12 0x3E6F7344 -#define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF -#define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103 -#define CTOP_INST_SCHD_RW 0x3E6F7004 -#define CTOP_INST_SCHD_RD 0x3E6F7084 -#define CTOP_INST_ASRI_0_R3 0x3B56003E -#define CTOP_INST_XEX_DI_R2_R2_R3 0x4A664C00 -#define CTOP_INST_EXC_DI_R2_R2_R3 0x4A664C01 -#define CTOP_INST_AADD_DI_R2_R2_R3 0x4A664C02 -#define CTOP_INST_AAND_DI_R2_R2_R3 0x4A664C04 -#define CTOP_INST_AOR_DI_R2_R2_R3 0x4A664C05 -#define CTOP_INST_AXOR_DI_R2_R2_R3 0x4A664C06 - -/* Do not use D$ for address in 2G-3G */ -#define HW_COMPLY_KRN_NOT_D_CACHED BIT(28) - -#define NPS_MSU_EN_CFG 0x80 -#define NPS_CRG_BLKID 0x480 -#define NPS_CRG_SYNC_BIT BIT(0) -#define NPS_GIM_BLKID 0x5C0 - -/* GIM registers and fields*/ -#define NPS_GIM_UART_LINE BIT(7) -#define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE BIT(10) -#define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE BIT(11) -#define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE BIT(25) -#define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE BIT(26) - -#ifndef __ASSEMBLY__ -/* Functional registers definition */ -struct nps_host_reg_mtm_cfg { - union { - struct { - u32 gen:1, gdis:1, clk_gate_dis:1, asb:1, - __reserved:9, nat:3, ten:16; - }; - u32 value; - }; -}; - -struct nps_host_reg_mtm_cpu_cfg { - union { - struct { - u32 csa:22, dmsid:6, __reserved:3, cs:1; - }; - u32 value; - }; -}; - -struct nps_host_reg_thr_init { - union { - struct { - u32 str:1, __reserved:27, thr_id:4; - }; - u32 value; - }; -}; - -struct nps_host_reg_thr_init_sts { - union { - struct { - u32 bsy:1, err:1, __reserved:26, thr_id:4; - }; - u32 value; - }; -}; - -struct nps_host_reg_msu_en_cfg { - union { - struct { - u32 __reserved1:11, - rtc_en:1, ipc_en:1, gim_1_en:1, - gim_0_en:1, ipi_en:1, buff_e_rls_bmuw:1, - buff_e_alc_bmuw:1, buff_i_rls_bmuw:1, buff_i_alc_bmuw:1, - buff_e_rls_bmue:1, buff_e_alc_bmue:1, buff_i_rls_bmue:1, - buff_i_alc_bmue:1, __reserved2:1, buff_e_pre_en:1, - buff_i_pre_en:1, pmuw_ja_en:1, pmue_ja_en:1, - pmuw_nj_en:1, pmue_nj_en:1, msu_en:1; - }; - u32 value; - }; -}; - -struct nps_host_reg_gim_p_int_dst { - union { - struct { - u32 int_out_en:1, __reserved1:4, - is:1, intm:2, __reserved2:4, - nid:4, __reserved3:4, cid:4, - __reserved4:4, tid:4; - }; - u32 value; - }; -}; - -/* AUX registers definition */ -struct nps_host_reg_aux_dpc { - union { - struct { - u32 ien:1, men:1, hen:1, reserved:29; - }; - u32 value; - }; -}; - -struct nps_host_reg_aux_udmc { - union { - struct { - u32 dcp:1, cme:1, __reserved:19, nat:3, - __reserved2:5, dcas:3; - }; - u32 value; - }; -}; - -struct nps_host_reg_aux_mt_ctrl { - union { - struct { - u32 mten:1, hsen:1, scd:1, sten:1, - st_cnt:8, __reserved:8, - hs_cnt:8, __reserved1:4; - }; - u32 value; - }; -}; - -struct nps_host_reg_aux_hw_comply { - union { - struct { - u32 me:1, le:1, te:1, knc:1, __reserved:28; - }; - u32 value; - }; -}; - -struct nps_host_reg_aux_lpc { - union { - struct { - u32 mep:1, __reserved:31; - }; - u32 value; - }; -}; - -/* CRG registers */ -#define REG_GEN_PURP_0 nps_host_reg_non_cl(NPS_CRG_BLKID, 0x1BF) - -/* GIM registers */ -#define REG_GIM_P_INT_EN_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x100) -#define REG_GIM_P_INT_POL_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x110) -#define REG_GIM_P_INT_SENS_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x114) -#define REG_GIM_P_INT_BLK_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x118) -#define REG_GIM_P_INT_DST_10 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13A) -#define REG_GIM_P_INT_DST_11 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13B) -#define REG_GIM_P_INT_DST_25 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x149) -#define REG_GIM_P_INT_DST_26 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x14A) - -#else - -.macro GET_CPU_ID reg - lr \reg, [CTOP_AUX_LOGIC_GLOBAL_ID] -#ifndef CONFIG_EZNPS_MTM_EXT - lsr \reg, \reg, 4 -#endif -.endm - -#endif /* __ASSEMBLY__ */ - -#endif /* _PLAT_EZNPS_CTOP_H */ diff --git a/arch/arc/plat-eznps/include/plat/mtm.h b/arch/arc/plat-eznps/include/plat/mtm.h deleted file mode 100644 index 7c55becc891b..000000000000 --- a/arch/arc/plat-eznps/include/plat/mtm.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright(c) 2015 EZchip Technologies. - */ - -#ifndef _PLAT_EZNPS_MTM_H -#define _PLAT_EZNPS_MTM_H - -#include - -static inline void *nps_mtm_reg_addr(u32 cpu, u32 reg) -{ - struct global_id gid; - u32 core, blkid; - - gid.value = cpu; - core = gid.core; - blkid = (((core & 0x0C) << 2) | (core & 0x03)); - - return nps_host_reg(cpu, blkid, reg); -} - -#ifdef CONFIG_EZNPS_MTM_EXT -#define NPS_CPU_TO_THREAD_NUM(cpu) \ - ({ struct global_id gid; gid.value = cpu; gid.thread; }) - -/* MTM registers */ -#define MTM_CFG(cpu) nps_mtm_reg_addr(cpu, 0x81) -#define MTM_THR_INIT(cpu) nps_mtm_reg_addr(cpu, 0x92) -#define MTM_THR_INIT_STS(cpu) nps_mtm_reg_addr(cpu, 0x93) - -#define get_thread(map) map.thread -#define eznps_max_cpus 4096 -#define eznps_cpus_per_cluster 256 - -void mtm_enable_core(unsigned int cpu); -int mtm_enable_thread(int cpu); -#else /* !CONFIG_EZNPS_MTM_EXT */ - -#define get_thread(map) 0 -#define eznps_max_cpus 256 -#define eznps_cpus_per_cluster 16 -#define mtm_enable_core(cpu) -#define mtm_enable_thread(cpu) 1 -#define NPS_CPU_TO_THREAD_NUM(cpu) 0 - -#endif /* CONFIG_EZNPS_MTM_EXT */ - -#endif /* _PLAT_EZNPS_MTM_H */ diff --git a/arch/arc/plat-eznps/include/plat/smp.h b/arch/arc/plat-eznps/include/plat/smp.h deleted file mode 100644 index e433f118bdca..000000000000 --- a/arch/arc/plat-eznps/include/plat/smp.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright(c) 2015 EZchip Technologies. - */ - -#ifndef __PLAT_EZNPS_SMP_H -#define __PLAT_EZNPS_SMP_H - -#ifdef CONFIG_SMP - -extern void res_service(void); - -#endif /* CONFIG_SMP */ - -#endif diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c deleted file mode 100644 index 3dcf5a9e2976..000000000000 --- a/arch/arc/plat-eznps/mtm.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright(c) 2015 EZchip Technologies. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define MT_HS_CNT_MIN 0x01 -#define MT_HS_CNT_MAX 0xFF -#define MT_CTRL_ST_CNT 0xF -#define NPS_NUM_HW_THREADS 0x10 - -static int mtm_hs_ctr = MT_HS_CNT_MAX; - -#ifdef CONFIG_EZNPS_MEM_ERROR_ALIGN -int do_memory_error(unsigned long address, struct pt_regs *regs) -{ - die("Invalid Mem Access", regs, address); - - return 1; -} -#endif - -static void mtm_init_nat(int cpu) -{ - struct nps_host_reg_mtm_cfg mtm_cfg; - struct nps_host_reg_aux_udmc udmc; - int log_nat, nat = 0, i, t; - - /* Iterate core threads and update nat */ - for (i = 0, t = cpu; i < NPS_NUM_HW_THREADS; i++, t++) - nat += test_bit(t, cpumask_bits(cpu_possible_mask)); - - log_nat = ilog2(nat); - - udmc.value = read_aux_reg(CTOP_AUX_UDMC); - udmc.nat = log_nat; - write_aux_reg(CTOP_AUX_UDMC, udmc.value); - - mtm_cfg.value = ioread32be(MTM_CFG(cpu)); - mtm_cfg.nat = log_nat; - iowrite32be(mtm_cfg.value, MTM_CFG(cpu)); -} - -static void mtm_init_thread(int cpu) -{ - int i, tries = 5; - struct nps_host_reg_thr_init thr_init; - struct nps_host_reg_thr_init_sts thr_init_sts; - - /* Set thread init register */ - thr_init.value = 0; - iowrite32be(thr_init.value, MTM_THR_INIT(cpu)); - thr_init.thr_id = NPS_CPU_TO_THREAD_NUM(cpu); - thr_init.str = 1; - iowrite32be(thr_init.value, MTM_THR_INIT(cpu)); - - /* Poll till thread init is done */ - for (i = 0; i < tries; i++) { - thr_init_sts.value = ioread32be(MTM_THR_INIT_STS(cpu)); - if (thr_init_sts.thr_id == thr_init.thr_id) { - if (thr_init_sts.bsy) - continue; - else if (thr_init_sts.err) - pr_warn("Failed to thread init cpu %u\n", cpu); - break; - } - - pr_warn("Wrong thread id in thread init for cpu %u\n", cpu); - break; - } - - if (i == tries) - pr_warn("Got thread init timeout for cpu %u\n", cpu); -} - -int mtm_enable_thread(int cpu) -{ - struct nps_host_reg_mtm_cfg mtm_cfg; - - if (NPS_CPU_TO_THREAD_NUM(cpu) == 0) - return 1; - - /* Enable thread in mtm */ - mtm_cfg.value = ioread32be(MTM_CFG(cpu)); - mtm_cfg.ten |= (1 << (NPS_CPU_TO_THREAD_NUM(cpu))); - iowrite32be(mtm_cfg.value, MTM_CFG(cpu)); - - return 0; -} - -void mtm_enable_core(unsigned int cpu) -{ - int i; - struct nps_host_reg_aux_mt_ctrl mt_ctrl; - struct nps_host_reg_mtm_cfg mtm_cfg; - struct nps_host_reg_aux_dpc dpc; - - /* - * Initializing dpc register in each CPU. - * Overwriting the init value of the DPC - * register so that CMEM and FMT virtual address - * spaces are accessible, and Data Plane HW - * facilities are enabled. - */ - dpc.ien = 1; - dpc.men = 1; - write_aux_reg(CTOP_AUX_DPC, dpc.value); - - if (NPS_CPU_TO_THREAD_NUM(cpu) != 0) - return; - - /* Initialize Number of Active Threads */ - mtm_init_nat(cpu); - - /* Initialize mtm_cfg */ - mtm_cfg.value = ioread32be(MTM_CFG(cpu)); - mtm_cfg.ten = 1; - iowrite32be(mtm_cfg.value, MTM_CFG(cpu)); - - /* Initialize all other threads in core */ - for (i = 1; i < NPS_NUM_HW_THREADS; i++) - mtm_init_thread(cpu + i); - - - /* Enable HW schedule, stall counter, mtm */ - mt_ctrl.value = 0; - mt_ctrl.hsen = 1; - mt_ctrl.hs_cnt = mtm_hs_ctr; - mt_ctrl.mten = 1; - write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value); - - /* - * HW scheduling mechanism will start working - * Only after call to instruction "schd.rw". - * cpu_relax() calls "schd.rw" instruction. - */ - cpu_relax(); -} - -/* Verify and set the value of the mtm hs counter */ -static int __init set_mtm_hs_ctr(char *ctr_str) -{ - int hs_ctr; - int ret; - - ret = kstrtoint(ctr_str, 0, &hs_ctr); - - if (ret || hs_ctr > MT_HS_CNT_MAX || hs_ctr < MT_HS_CNT_MIN) { - pr_err("** Invalid @nps_mtm_hs_ctr [%d] needs to be [%d:%d] (incl)\n", - hs_ctr, MT_HS_CNT_MIN, MT_HS_CNT_MAX); - return -EINVAL; - } - - mtm_hs_ctr = hs_ctr; - - return 0; -} -early_param("nps_mtm_hs_ctr", set_mtm_hs_ctr); diff --git a/arch/arc/plat-eznps/platform.c b/arch/arc/plat-eznps/platform.c deleted file mode 100644 index 6de2fe840043..000000000000 --- a/arch/arc/plat-eznps/platform.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright(c) 2015 EZchip Technologies. - */ - -#include -#include -#include -#include - -static void __init eznps_configure_msu(void) -{ - int cpu; - struct nps_host_reg_msu_en_cfg msu_en_cfg = {.value = 0}; - - msu_en_cfg.msu_en = 1; - msu_en_cfg.ipi_en = 1; - msu_en_cfg.gim_0_en = 1; - msu_en_cfg.gim_1_en = 1; - - /* enable IPI and GIM messages on all clusters */ - for (cpu = 0 ; cpu < eznps_max_cpus; cpu += eznps_cpus_per_cluster) - iowrite32be(msu_en_cfg.value, - nps_host_reg(cpu, NPS_MSU_BLKID, NPS_MSU_EN_CFG)); -} - -static void __init eznps_configure_gim(void) -{ - u32 reg_value; - u32 gim_int_lines; - struct nps_host_reg_gim_p_int_dst gim_p_int_dst = {.value = 0}; - - gim_int_lines = NPS_GIM_UART_LINE; - gim_int_lines |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE; - gim_int_lines |= NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE; - gim_int_lines |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE; - gim_int_lines |= NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE; - - /* - * IRQ polarity - * low or high level - * negative or positive edge - */ - reg_value = ioread32be(REG_GIM_P_INT_POL_0); - reg_value &= ~gim_int_lines; - iowrite32be(reg_value, REG_GIM_P_INT_POL_0); - - /* IRQ type level or edge */ - reg_value = ioread32be(REG_GIM_P_INT_SENS_0); - reg_value |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE; - reg_value |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE; - iowrite32be(reg_value, REG_GIM_P_INT_SENS_0); - - /* - * GIM interrupt select type for - * dbg_lan TX and RX interrupts - * should be type 1 - * type 0 = IRQ line 6 - * type 1 = IRQ line 7 - */ - gim_p_int_dst.is = 1; - iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_10); - iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_11); - iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_25); - iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_26); - - /* - * CTOP IRQ lines should be defined - * as blocking in GIM - */ - iowrite32be(gim_int_lines, REG_GIM_P_INT_BLK_0); - - /* enable CTOP IRQ lines in GIM */ - iowrite32be(gim_int_lines, REG_GIM_P_INT_EN_0); -} - -static void __init eznps_early_init(void) -{ - eznps_configure_msu(); - eznps_configure_gim(); -} - -static const char *eznps_compat[] __initconst = { - "ezchip,arc-nps", - NULL, -}; - -MACHINE_START(NPS, "nps") - .dt_compat = eznps_compat, - .init_early = eznps_early_init, -MACHINE_END diff --git a/arch/arc/plat-eznps/smp.c b/arch/arc/plat-eznps/smp.c deleted file mode 100644 index f119cb7de2ae..000000000000 --- a/arch/arc/plat-eznps/smp.c +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright(c) 2015 EZchip Technologies. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define NPS_DEFAULT_MSID 0x34 -#define NPS_MTM_CPU_CFG 0x90 - -static char smp_cpuinfo_buf[128] = {"Extn [EZNPS-SMP]\t: On\n"}; - -/* Get cpu map from device tree */ -static int __init eznps_get_map(const char *name, struct cpumask *cpumask) -{ - unsigned long dt_root = of_get_flat_dt_root(); - const char *buf; - - buf = of_get_flat_dt_prop(dt_root, name, NULL); - if (!buf) - return 1; - - cpulist_parse(buf, cpumask); - - return 0; -} - -/* Update board cpu maps */ -static void __init eznps_init_cpumasks(void) -{ - struct cpumask cpumask; - - if (eznps_get_map("present-cpus", &cpumask)) { - pr_err("Failed to get present-cpus from dtb"); - return; - } - init_cpu_present(&cpumask); - - if (eznps_get_map("possible-cpus", &cpumask)) { - pr_err("Failed to get possible-cpus from dtb"); - return; - } - init_cpu_possible(&cpumask); -} - -static void eznps_init_core(unsigned int cpu) -{ - u32 sync_value; - struct nps_host_reg_aux_hw_comply hw_comply; - struct nps_host_reg_aux_lpc lpc; - - if (NPS_CPU_TO_THREAD_NUM(cpu) != 0) - return; - - hw_comply.value = read_aux_reg(CTOP_AUX_HW_COMPLY); - hw_comply.me = 1; - hw_comply.le = 1; - hw_comply.te = 1; - write_aux_reg(CTOP_AUX_HW_COMPLY, hw_comply.value); - - /* Enable MMU clock */ - lpc.mep = 1; - write_aux_reg(CTOP_AUX_LPC, lpc.value); - - /* Boot CPU only */ - if (!cpu) { - /* Write to general purpose register in CRG */ - sync_value = ioread32be(REG_GEN_PURP_0); - sync_value |= NPS_CRG_SYNC_BIT; - iowrite32be(sync_value, REG_GEN_PURP_0); - } -} - -/* - * Master kick starting another CPU - */ -static void __init eznps_smp_wakeup_cpu(int cpu, unsigned long pc) -{ - struct nps_host_reg_mtm_cpu_cfg cpu_cfg; - - if (mtm_enable_thread(cpu) == 0) - return; - - /* set PC, dmsid, and start CPU */ - cpu_cfg.value = (u32)res_service; - cpu_cfg.dmsid = NPS_DEFAULT_MSID; - cpu_cfg.cs = 1; - iowrite32be(cpu_cfg.value, nps_mtm_reg_addr(cpu, NPS_MTM_CPU_CFG)); -} - -static void eznps_ipi_send(int cpu) -{ - struct global_id gid; - struct { - union { - struct { - u32 num:8, cluster:8, core:8, thread:8; - }; - u32 value; - }; - } ipi; - - gid.value = cpu; - ipi.thread = get_thread(gid); - ipi.core = gid.core; - ipi.cluster = nps_cluster_logic_to_phys(gid.cluster); - ipi.num = NPS_IPI_IRQ; - - __asm__ __volatile__( - " mov r3, %0\n" - " .word %1\n" - : - : "r"(ipi.value), "i"(CTOP_INST_ASRI_0_R3) - : "r3"); -} - -static void eznps_init_per_cpu(int cpu) -{ - smp_ipi_irq_setup(cpu, NPS_IPI_IRQ); - - eznps_init_core(cpu); - mtm_enable_core(cpu); -} - -struct plat_smp_ops plat_smp_ops = { - .info = smp_cpuinfo_buf, - .init_early_smp = eznps_init_cpumasks, - .cpu_kick = eznps_smp_wakeup_cpu, - .ipi_send = eznps_ipi_send, - .init_per_cpu = eznps_init_per_cpu, -}; diff --git a/arch/arc/plat-hsdk/Kconfig b/arch/arc/plat-hsdk/Kconfig index ce8101834518..6b5c54576f54 100644 --- a/arch/arc/plat-hsdk/Kconfig +++ b/arch/arc/plat-hsdk/Kconfig @@ -8,5 +8,6 @@ menuconfig ARC_SOC_HSDK select ARC_HAS_ACCL_REGS select ARC_IRQ_NO_AUTOSAVE select CLK_HSDK + select RESET_CONTROLLER select RESET_HSDK select HAVE_PCI diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 80000a66a4e3..87912e5c2256 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1546,6 +1546,17 @@ config DEBUG_SIRFSOC_UART bool depends on ARCH_SIRF +config DEBUG_UART_FLOW_CONTROL + bool "Enable flow control (CTS) for the debug UART" + depends on DEBUG_LL + default y if ARCH_EBSA110 || DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC + help + Some UART ports are connected to terminals that will use modem + control signals to indicate whether they are ready to receive text. + In practice this means that the terminal is asserting the special + control signal CTS (Clear To Send). If your debug UART supports + this and your debug terminal will require it, enable this option. + config DEBUG_LL_INCLUDE string default "debug/sa1100.S" if DEBUG_SA1100 @@ -1893,11 +1904,6 @@ config DEBUG_UART_8250_PALMCHIP except for having a different register layout. Say Y here if the debug UART is of this type. -config DEBUG_UART_8250_FLOW_CONTROL - bool "Enable flow control for 8250 UART" - depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 - default y if ARCH_EBSA110 || DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC - config DEBUG_UNCOMPRESS bool "Enable decompressor debugging via DEBUG_LL output" depends on ARCH_MULTIPLATFORM || PLAT_SAMSUNG || ARM_SINGLE_ARMV7M diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e589da3c8949..c4301437ca72 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -143,6 +143,9 @@ head-y := arch/arm/kernel/head$(MMUEXT).o # Text offset. This list is sorted numerically by address in order to # provide a means to avoid/resolve conflicts in multi-arch kernels. +# Note: the 32kB below this value is reserved for use by the kernel +# during boot, and this offset is critical to the functioning of +# kexec-tools. textofs-y := 0x00008000 # We don't want the htc bootloader to corrupt kernel during resume textofs-$(CONFIG_PM_H1940) := 0x00108000 diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 58028abd05d9..47f001ca5499 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -7,11 +7,11 @@ OBJS = -AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) HEAD = head.o OBJS += misc.o decompress.o ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y) OBJS += debug.o +AFLAGS_head.o += -DDEBUG endif FONTC = $(srctree)/lib/fonts/font_acorn_8x8.c @@ -68,7 +68,12 @@ ZTEXTADDR := 0 ZBSSADDR := ALIGN(8) endif +MALLOC_SIZE := 65536 + +AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) -DMALLOC_SIZE=$(MALLOC_SIZE) CPPFLAGS_vmlinux.lds := -DTEXT_START="$(ZTEXTADDR)" -DBSS_START="$(ZBSSADDR)" +CPPFLAGS_vmlinux.lds += -DTEXT_OFFSET="$(TEXT_OFFSET)" +CPPFLAGS_vmlinux.lds += -DMALLOC_SIZE="$(MALLOC_SIZE)" compress-$(CONFIG_KERNEL_GZIP) = gzip compress-$(CONFIG_KERNEL_LZO) = lzo diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S index 6bf2917a4621..fac40a717fcf 100644 --- a/arch/arm/boot/compressed/debug.S +++ b/arch/arm/boot/compressed/debug.S @@ -8,7 +8,10 @@ ENTRY(putc) addruart r1, r2, r3 - waituart r3, r1 +#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL + waituartcts r3, r1 +#endif + waituarttxrdy r3, r1 senduart r0, r1 busyuart r3, r1 mov pc, lr diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 434a16982e34..2e04ec5b5446 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -28,19 +28,19 @@ #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) .macro loadsp, rb, tmp1, tmp2 .endm - .macro writeb, ch, rb + .macro writeb, ch, rb, tmp mcr p14, 0, \ch, c0, c5, 0 .endm #elif defined(CONFIG_CPU_XSCALE) .macro loadsp, rb, tmp1, tmp2 .endm - .macro writeb, ch, rb + .macro writeb, ch, rb, tmp mcr p14, 0, \ch, c8, c0, 0 .endm #else .macro loadsp, rb, tmp1, tmp2 .endm - .macro writeb, ch, rb + .macro writeb, ch, rb, tmp mcr p14, 0, \ch, c1, c0, 0 .endm #endif @@ -49,8 +49,13 @@ #include CONFIG_DEBUG_LL_INCLUDE - .macro writeb, ch, rb + .macro writeb, ch, rb, tmp +#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL + waituartcts \tmp, \rb +#endif + waituarttxrdy \tmp, \rb senduart \ch, \rb + busyuart \tmp, \rb .endm #if defined(CONFIG_ARCH_SA1100) @@ -81,42 +86,11 @@ bl phex .endm - .macro debug_reloc_start -#ifdef DEBUG - kputc #'\n' - kphex r6, 8 /* processor id */ - kputc #':' - kphex r7, 8 /* architecture id */ -#ifdef CONFIG_CPU_CP15 - kputc #':' - mrc p15, 0, r0, c1, c0 - kphex r0, 8 /* control reg */ -#endif - kputc #'\n' - kphex r5, 8 /* decompressed kernel start */ - kputc #'-' - kphex r9, 8 /* decompressed kernel end */ - kputc #'>' - kphex r4, 8 /* kernel execution address */ - kputc #'\n' -#endif - .endm - - .macro debug_reloc_end -#ifdef DEBUG - kphex r5, 8 /* end of kernel */ - kputc #'\n' - mov r0, r4 - bl memdump /* dump 256 bytes at start of kernel */ -#endif - .endm - /* * Debug kernel copy by printing the memory addresses involved */ .macro dbgkc, begin, end, cbegin, cend #ifdef DEBUG - kputc #'\n' kputc #'C' kputc #':' kputc #'0' @@ -136,7 +110,28 @@ kputc #'x' kphex \cend, 8 /* End of kernel copy */ kputc #'\n' - kputc #'\r' +#endif + .endm + + /* + * Debug print of the final appended DTB location + */ + .macro dbgadtb, begin, end +#ifdef DEBUG + kputc #'D' + kputc #'T' + kputc #'B' + kputc #':' + kputc #'0' + kputc #'x' + kphex \begin, 8 /* Start of appended DTB */ + kputc #' ' + kputc #'(' + kputc #'0' + kputc #'x' + kphex \end, 8 /* End of appended DTB */ + kputc #')' + kputc #'\n' #endif .endm @@ -303,7 +298,7 @@ restart: adr r0, LC1 #ifndef CONFIG_ZBOOT_ROM /* malloc space is above the relocated stack (64k max) */ - add r10, sp, #0x10000 + add r10, sp, #MALLOC_SIZE #else /* * With ZBOOT_ROM the bss/stack is non relocatable, @@ -357,6 +352,7 @@ restart: adr r0, LC1 mov r5, r5, ror #8 eor r5, r5, r1, lsr #8 #endif + dbgadtb r6, r5 /* 50% DTB growth should be good enough */ add r5, r5, r5, lsr #1 /* preserve 64-bit alignment */ @@ -614,7 +610,7 @@ not_relocated: mov r0, #0 */ mov r0, r4 mov r1, sp @ malloc space above stack - add r2, sp, #0x10000 @ 64k max + add r2, sp, #MALLOC_SIZE @ 64k max mov r3, r7 bl decompress_kernel @@ -1356,7 +1352,7 @@ puts: loadsp r3, r2, r1 1: ldrb r2, [r0], #1 teq r2, #0 moveq pc, lr -2: writeb r2, r3 +2: writeb r2, r3, r1 mov r1, #0x00020000 3: subs r1, r1, #1 bne 3b diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S index b914be3a207b..1bcb68ac4b01 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.S +++ b/arch/arm/boot/compressed/vmlinux.lds.S @@ -44,10 +44,12 @@ SECTIONS } .table : ALIGN(4) { _table_start = .; - LONG(ZIMAGE_MAGIC(4)) + LONG(ZIMAGE_MAGIC(6)) LONG(ZIMAGE_MAGIC(0x5a534c4b)) LONG(ZIMAGE_MAGIC(__piggy_size_addr - _start)) LONG(ZIMAGE_MAGIC(_kernel_bss_size)) + LONG(ZIMAGE_MAGIC(TEXT_OFFSET)) + LONG(ZIMAGE_MAGIC(MALLOC_SIZE)) LONG(0) _table_end = .; } diff --git a/arch/arm/include/debug/8250.S b/arch/arm/include/debug/8250.S index e4a036f082c2..e3692a37cede 100644 --- a/arch/arm/include/debug/8250.S +++ b/arch/arm/include/debug/8250.S @@ -45,10 +45,11 @@ bne 1002b .endm - .macro waituart,rd,rx -#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL + .macro waituarttxrdy,rd,rx + .endm + + .macro waituartcts,rd,rx 1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] tst \rd, #UART_MSR_CTS beq 1001b -#endif .endm diff --git a/arch/arm/include/debug/asm9260.S b/arch/arm/include/debug/asm9260.S index 0da1eb625331..5a0ce145c44a 100644 --- a/arch/arm/include/debug/asm9260.S +++ b/arch/arm/include/debug/asm9260.S @@ -11,7 +11,10 @@ ldr \rv, = CONFIG_DEBUG_UART_VIRT .endm - .macro waituart,rd,rx + .macro waituarttxrdy,rd,rx + .endm + + .macro waituartcts,rd,rx .endm .macro senduart,rd,rx diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S index 6c91cbaaa20b..17722824e2f2 100644 --- a/arch/arm/include/debug/at91.S +++ b/arch/arm/include/debug/at91.S @@ -19,12 +19,15 @@ strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register .endm - .macro waituart,rd,rx + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit beq 1001b .endm + .macro waituartcts,rd,rx + .endm + .macro busyuart,rd,rx 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete diff --git a/arch/arm/include/debug/bcm63xx.S b/arch/arm/include/debug/bcm63xx.S index 06a896227396..da65abb6738d 100644 --- a/arch/arm/include/debug/bcm63xx.S +++ b/arch/arm/include/debug/bcm63xx.S @@ -17,12 +17,15 @@ strb \rd, [\rx, #UART_FIFO_REG] .endm - .macro waituart, rd, rx + .macro waituarttxrdy, rd, rx 1001: ldr \rd, [\rx, #UART_IR_REG] tst \rd, #(1 << UART_IR_TXEMPTY) beq 1001b .endm + .macro waituartcts, rd, rx + .endm + .macro busyuart, rd, rx 1002: ldr \rd, [\rx, #UART_IR_REG] tst \rd, #(1 << UART_IR_TXTRESH) diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S index 132a20c4a676..7ffe66993029 100644 --- a/arch/arm/include/debug/brcmstb.S +++ b/arch/arm/include/debug/brcmstb.S @@ -142,7 +142,10 @@ ARM_BE8( rev \rd, \rd ) bne 1002b .endm - .macro waituart,rd,rx + .macro waituarttxrdy,rd,rx + .endm + + .macro waituartcts,rd,rx .endm /* diff --git a/arch/arm/include/debug/clps711x.S b/arch/arm/include/debug/clps711x.S index 774a67ac3877..a983d12a6515 100644 --- a/arch/arm/include/debug/clps711x.S +++ b/arch/arm/include/debug/clps711x.S @@ -20,7 +20,10 @@ ldr \rp, =CLPS711X_UART_PADDR .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm .macro senduart,rd,rx diff --git a/arch/arm/include/debug/dc21285.S b/arch/arm/include/debug/dc21285.S index d7e8c71706ab..4ec0e5e31704 100644 --- a/arch/arm/include/debug/dc21285.S +++ b/arch/arm/include/debug/dc21285.S @@ -34,5 +34,8 @@ bne 1001b .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm diff --git a/arch/arm/include/debug/digicolor.S b/arch/arm/include/debug/digicolor.S index 256f5f4da275..443674cad76a 100644 --- a/arch/arm/include/debug/digicolor.S +++ b/arch/arm/include/debug/digicolor.S @@ -21,7 +21,10 @@ strb \rd, [\rx, #UA0_EMI_REC] .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm .macro busyuart,rd,rx diff --git a/arch/arm/include/debug/efm32.S b/arch/arm/include/debug/efm32.S index 5ed5028306f4..b0083d6e31e8 100644 --- a/arch/arm/include/debug/efm32.S +++ b/arch/arm/include/debug/efm32.S @@ -29,7 +29,10 @@ strb \rd, [\rx, #UARTn_TXDATA] .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #UARTn_STATUS] tst \rd, #UARTn_STATUS_TXBL beq 1001b diff --git a/arch/arm/include/debug/icedcc.S b/arch/arm/include/debug/icedcc.S index 74a0dd036a17..d5e65da8a687 100644 --- a/arch/arm/include/debug/icedcc.S +++ b/arch/arm/include/debug/icedcc.S @@ -23,7 +23,10 @@ beq 1001b .endm - .macro waituart, rd, rx + .macro waituartcts, rd, rx + .endm + + .macro waituarttxrdy, rd, rx mov \rd, #0x2000000 1001: subs \rd, \rd, #1 @@ -47,7 +50,10 @@ beq 1001b .endm - .macro waituart, rd, rx + .macro waituartcts, rd, rx + .endm + + .macro waituarttxrdy, rd, rx mov \rd, #0x10000000 1001: subs \rd, \rd, #1 @@ -72,7 +78,10 @@ .endm - .macro waituart, rd, rx + .macro waituartcts, rd, rx + .endm + + .macro waituarttxrdy, rd, rx mov \rd, #0x2000000 1001: subs \rd, \rd, #1 diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S index 1c1b9d1da4c8..bb7b9550580c 100644 --- a/arch/arm/include/debug/imx.S +++ b/arch/arm/include/debug/imx.S @@ -35,7 +35,10 @@ str \rd, [\rx, #0x40] @ TXDATA .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm .macro busyuart,rd,rx diff --git a/arch/arm/include/debug/meson.S b/arch/arm/include/debug/meson.S index 1e501a0054ae..7b60e4401225 100644 --- a/arch/arm/include/debug/meson.S +++ b/arch/arm/include/debug/meson.S @@ -25,7 +25,10 @@ beq 1002b .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS] tst \rd, #MESON_AO_UART_TX_FIFO_FULL bne 1001b diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S index 9405b71461da..530edc74f9a3 100644 --- a/arch/arm/include/debug/msm.S +++ b/arch/arm/include/debug/msm.S @@ -17,7 +17,10 @@ ARM_BE8(rev \rd, \rd ) str \rd, [\rx, #0x70] .endm - .macro waituart, rd, rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy, rd, rx @ check for TX_EMT in UARTDM_SR ldr \rd, [\rx, #0x08] ARM_BE8(rev \rd, \rd ) diff --git a/arch/arm/include/debug/omap2plus.S b/arch/arm/include/debug/omap2plus.S index b5696a33ba0f..0680be6c79d3 100644 --- a/arch/arm/include/debug/omap2plus.S +++ b/arch/arm/include/debug/omap2plus.S @@ -75,5 +75,8 @@ omap_uart_lsr: .word 0 bne 1001b .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm diff --git a/arch/arm/include/debug/pl01x.S b/arch/arm/include/debug/pl01x.S index a2a553afe7b8..0c7bfa4c10db 100644 --- a/arch/arm/include/debug/pl01x.S +++ b/arch/arm/include/debug/pl01x.S @@ -26,7 +26,10 @@ strb \rd, [\rx, #UART01x_DR] .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #UART01x_FR] ARM_BE8( rev \rd, \rd ) tst \rd, #UART01x_FR_TXFF diff --git a/arch/arm/include/debug/renesas-scif.S b/arch/arm/include/debug/renesas-scif.S index 25f06663a9a4..8e433e981bbe 100644 --- a/arch/arm/include/debug/renesas-scif.S +++ b/arch/arm/include/debug/renesas-scif.S @@ -33,7 +33,10 @@ ldr \rv, =SCIF_VIRT .endm - .macro waituart, rd, rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy, rd, rx 1001: ldrh \rd, [\rx, #FSR] tst \rd, #TDFE beq 1001b diff --git a/arch/arm/include/debug/sa1100.S b/arch/arm/include/debug/sa1100.S index 6109e6058e5b..7968ea52df3d 100644 --- a/arch/arm/include/debug/sa1100.S +++ b/arch/arm/include/debug/sa1100.S @@ -51,7 +51,10 @@ str \rd, [\rx, #UTDR] .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #UTSR1] tst \rd, #UTSR1_TNF beq 1001b diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S index 69201d7fb48f..ab474d564a90 100644 --- a/arch/arm/include/debug/samsung.S +++ b/arch/arm/include/debug/samsung.S @@ -69,7 +69,10 @@ ARM_BE8(rev \rd, \rd) 1002: @ exit busyuart .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx ldr \rd, [\rx, # S3C2410_UFCON] ARM_BE8(rev \rd, \rd) tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? diff --git a/arch/arm/include/debug/sirf.S b/arch/arm/include/debug/sirf.S index e73e4de0a015..3612c7b9cbe7 100644 --- a/arch/arm/include/debug/sirf.S +++ b/arch/arm/include/debug/sirf.S @@ -29,7 +29,10 @@ .macro busyuart,rd,rx .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS] tst \rd, #SIRF_LLUART_TXFIFO_EMPTY beq 1001b diff --git a/arch/arm/include/debug/sti.S b/arch/arm/include/debug/sti.S index 6b42c91f217d..72d052511890 100644 --- a/arch/arm/include/debug/sti.S +++ b/arch/arm/include/debug/sti.S @@ -45,7 +45,10 @@ strb \rd, [\rx, #ASC_TX_BUF_OFF] .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #ASC_STA_OFF] tst \rd, #ASC_STA_TX_FULL bne 1001b diff --git a/arch/arm/include/debug/stm32.S b/arch/arm/include/debug/stm32.S index f3c4a37210ed..b6d9df30e37d 100644 --- a/arch/arm/include/debug/stm32.S +++ b/arch/arm/include/debug/stm32.S @@ -27,7 +27,10 @@ strb \rd, [\rx, #STM32_USART_TDR_OFF] .endm -.macro waituart,rd,rx +.macro waituartcts,rd,rx +.endm + +.macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty beq 1001b diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S index 2148d0f88591..98daa7f48314 100644 --- a/arch/arm/include/debug/tegra.S +++ b/arch/arm/include/debug/tegra.S @@ -178,15 +178,16 @@ 1002: .endm - .macro waituart, rd, rx -#ifdef FLOW_CONTROL + .macro waituartcts, rd, rx cmp \rx, #0 beq 1002f 1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT] tst \rd, #UART_MSR_CTS beq 1001b 1002: -#endif + .endm + + .macro waituarttxrdy,rd,rx .endm /* diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S index 854d9bd82770..035bcbf117ab 100644 --- a/arch/arm/include/debug/vf.S +++ b/arch/arm/include/debug/vf.S @@ -29,5 +29,8 @@ beq 1001b @ wait until transmit done .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm diff --git a/arch/arm/include/debug/vt8500.S b/arch/arm/include/debug/vt8500.S index 8dc1df2d91b8..d01094fdbc8c 100644 --- a/arch/arm/include/debug/vt8500.S +++ b/arch/arm/include/debug/vt8500.S @@ -28,7 +28,10 @@ bne 1001b .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm #endif diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S index 58d77c972fd6..5d42cc35ecf3 100644 --- a/arch/arm/include/debug/zynq.S +++ b/arch/arm/include/debug/zynq.S @@ -33,7 +33,10 @@ strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #UART_SR_OFFSET] ARM_BE8( rev \rd, \rd ) tst \rd, #UART_SR_TXEMPTY diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index e112072b579d..d92f44bdf438 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -89,11 +89,18 @@ ENTRY(printascii) 2: teq r1, #'\n' bne 3f mov r1, #'\r' - waituart r2, r3 +#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL + waituartcts r2, r3 +#endif + waituarttxrdy r2, r3 senduart r1, r3 busyuart r2, r3 mov r1, #'\n' -3: waituart r2, r3 +3: +#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL + waituartcts r2, r3 +#endif + waituarttxrdy r2, r3 senduart r1, r3 busyuart r2, r3 b 1b diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 7a4853b1213a..08660ae9dcbc 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -683,6 +683,40 @@ static void disable_single_step(struct perf_event *bp) arch_install_hw_breakpoint(bp); } +/* + * Arm32 hardware does not always report a watchpoint hit address that matches + * one of the watchpoints set. It can also report an address "near" the + * watchpoint if a single instruction access both watched and unwatched + * addresses. There is no straight-forward way, short of disassembling the + * offending instruction, to map that address back to the watchpoint. This + * function computes the distance of the memory access from the watchpoint as a + * heuristic for the likelyhood that a given access triggered the watchpoint. + * + * See this same function in the arm64 platform code, which has the same + * problem. + * + * The function returns the distance of the address from the bytes watched by + * the watchpoint. In case of an exact match, it returns 0. + */ +static u32 get_distance_from_watchpoint(unsigned long addr, u32 val, + struct arch_hw_breakpoint_ctrl *ctrl) +{ + u32 wp_low, wp_high; + u32 lens, lene; + + lens = __ffs(ctrl->len); + lene = __fls(ctrl->len); + + wp_low = val + lens; + wp_high = val + lene; + if (addr < wp_low) + return wp_low - addr; + else if (addr > wp_high) + return addr - wp_high; + else + return 0; +} + static int watchpoint_fault_on_uaccess(struct pt_regs *regs, struct arch_hw_breakpoint *info) { @@ -692,23 +726,25 @@ static int watchpoint_fault_on_uaccess(struct pt_regs *regs, static void watchpoint_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { - int i, access; - u32 val, ctrl_reg, alignment_mask; + int i, access, closest_match = 0; + u32 min_dist = -1, dist; + u32 val, ctrl_reg; struct perf_event *wp, **slots; struct arch_hw_breakpoint *info; struct arch_hw_breakpoint_ctrl ctrl; slots = this_cpu_ptr(wp_on_reg); + /* + * Find all watchpoints that match the reported address. If no exact + * match is found. Attribute the hit to the closest watchpoint. + */ + rcu_read_lock(); for (i = 0; i < core_num_wrps; ++i) { - rcu_read_lock(); - wp = slots[i]; - if (wp == NULL) - goto unlock; + continue; - info = counter_arch_bp(wp); /* * The DFAR is an unknown value on debug architectures prior * to 7.1. Since we only allow a single watchpoint on these @@ -717,33 +753,31 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, */ if (debug_arch < ARM_DEBUG_ARCH_V7_1) { BUG_ON(i > 0); + info = counter_arch_bp(wp); info->trigger = wp->attr.bp_addr; } else { - if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) - alignment_mask = 0x7; - else - alignment_mask = 0x3; - - /* Check if the watchpoint value matches. */ - val = read_wb_reg(ARM_BASE_WVR + i); - if (val != (addr & ~alignment_mask)) - goto unlock; - - /* Possible match, check the byte address select. */ - ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); - decode_ctrl_reg(ctrl_reg, &ctrl); - if (!((1 << (addr & alignment_mask)) & ctrl.len)) - goto unlock; - /* Check that the access type matches. */ if (debug_exception_updates_fsr()) { access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W : HW_BREAKPOINT_R; if (!(access & hw_breakpoint_type(wp))) - goto unlock; + continue; } + val = read_wb_reg(ARM_BASE_WVR + i); + ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); + decode_ctrl_reg(ctrl_reg, &ctrl); + dist = get_distance_from_watchpoint(addr, val, &ctrl); + if (dist < min_dist) { + min_dist = dist; + closest_match = i; + } + /* Is this an exact match? */ + if (dist != 0) + continue; + /* We have a winner. */ + info = counter_arch_bp(wp); info->trigger = addr; } @@ -765,13 +799,23 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, * we can single-step over the watchpoint trigger. */ if (!is_default_overflow_handler(wp)) - goto unlock; - + continue; step: enable_single_step(wp, instruction_pointer(regs)); -unlock: - rcu_read_unlock(); } + + if (min_dist > 0 && min_dist != -1) { + /* No exact match found. */ + wp = slots[closest_match]; + info = counter_arch_bp(wp); + info->trigger = addr; + pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); + perf_bp_event(wp, regs); + if (is_default_overflow_handler(wp)) + enable_single_step(wp, instruction_pointer(regs)); + } + + rcu_read_unlock(); } static void watchpoint_single_step_handler(unsigned long pc) diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 3d2c108e911e..431709725d02 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -369,6 +369,15 @@ static struct pxaficp_platform_data tosa_ficp_platform_data = { /* * Tosa AC IN */ +static struct gpiod_lookup_table tosa_power_gpiod_table = { + .dev_id = "gpio-charger", + .table = { + GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_AC_IN, + NULL, GPIO_ACTIVE_LOW), + { }, + }, +}; + static char *tosa_ac_supplied_to[] = { "main-battery", "backup-battery", @@ -378,8 +387,6 @@ static char *tosa_ac_supplied_to[] = { static struct gpio_charger_platform_data tosa_power_data = { .name = "charger", .type = POWER_SUPPLY_TYPE_MAINS, - .gpio = TOSA_GPIO_AC_IN, - .gpio_active_low = 1, .supplied_to = tosa_ac_supplied_to, .num_supplicants = ARRAY_SIZE(tosa_ac_supplied_to), }; @@ -951,6 +958,7 @@ static void __init tosa_init(void) clk_add_alias("CLK_CK3P6MI", tc6393xb_device.name, "GPIO11_CLK", NULL); gpiod_add_lookup_table(&tosa_udc_gpiod_table); + gpiod_add_lookup_table(&tosa_power_gpiod_table); platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 3cc2b71e16f0..bd3a52fd09ce 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include