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perf/x86/intel: Track the num of events needs late setup
When a machine supports PEBS v6, perf unconditionally searches the cpuc->event_list[] for every event and check if the late setup is required, which is unnecessary. The late setup is only required for special events, e.g., events support counters snapshotting feature. Add n_late_setup to track the num of events that needs the late setup. Other features, e.g., auto counter reload feature, require the late setup as well. Add a wrapper, intel_pmu_pebs_late_setup, for the events that support counters snapshotting feature. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Thomas Falcon <thomas.falcon@intel.com> Link: https://lkml.kernel.org/r/20250327195217.2683619-3-kan.liang@linux.intel.com
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@ -2603,6 +2603,8 @@ static void intel_pmu_del_event(struct perf_event *event)
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intel_pmu_lbr_del(event);
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if (event->attr.precise_ip)
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intel_pmu_pebs_del(event);
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if (is_pebs_counter_event_group(event))
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this_cpu_ptr(&cpu_hw_events)->n_late_setup--;
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}
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static int icl_set_topdown_event_period(struct perf_event *event)
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@ -2914,12 +2916,24 @@ static void intel_pmu_enable_event(struct perf_event *event)
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}
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}
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void intel_pmu_late_setup(void)
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{
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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if (!cpuc->n_late_setup)
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return;
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intel_pmu_pebs_late_setup(cpuc);
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}
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static void intel_pmu_add_event(struct perf_event *event)
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{
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if (event->attr.precise_ip)
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intel_pmu_pebs_add(event);
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if (intel_pmu_needs_branch_stack(event))
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intel_pmu_lbr_add(event);
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if (is_pebs_counter_event_group(event))
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this_cpu_ptr(&cpu_hw_events)->n_late_setup++;
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}
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/*
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@ -1355,9 +1355,8 @@ static void __intel_pmu_pebs_update_cfg(struct perf_event *event,
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}
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static void intel_pmu_late_setup(void)
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void intel_pmu_pebs_late_setup(struct cpu_hw_events *cpuc)
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{
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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struct perf_event *event;
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u64 pebs_data_cfg = 0;
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int i;
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@ -261,6 +261,7 @@ struct cpu_hw_events {
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struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
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int n_excl; /* the number of exclusive events */
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int n_late_setup; /* the num of events needs late setup */
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unsigned int txn_flags;
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int is_fake;
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@ -1581,6 +1582,8 @@ void intel_pmu_disable_bts(void);
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int intel_pmu_drain_bts_buffer(void);
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void intel_pmu_late_setup(void);
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u64 grt_latency_data(struct perf_event *event, u64 status);
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u64 cmt_latency_data(struct perf_event *event, u64 status);
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@ -1637,6 +1640,8 @@ void intel_pmu_pebs_disable_all(void);
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void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in);
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void intel_pmu_pebs_late_setup(struct cpu_hw_events *cpuc);
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void intel_pmu_drain_pebs_buffer(void);
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void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr);
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