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UAPI Changes:

Browse Source 
- (Implicit) Fix the exec unnecessary implicit fencing (Matt Brost)
 
 Driver Changes:
 - Fix an inverted if statement (Colin)
 - Fixes around display d3cold vs non-d3cold runtime pm (Imre)
 - A couple of scheduling fixes (Matt Brost)
 - Increase a query timestamp witdh (Lucas)
 - Move a timestamp read (Lucas)
 - Tidy some code using multiple put_user() (Lucas)
 - Fix an ufence signaling error (Nirmoy)
 - Initialize the ufence.signalled field (Matt Auld)
 - Display fb alignement work (Juha-Pekka)
 - Disallow horisontal flip with tile4 + display20 (Juha-Pekka)
 - Extend a workaround (Shekhar)
 - Enlarge the global invalidation timeout (Shuicheng)
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Merge tag 'drm-xe-next-2024-10-17' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next

UAPI Changes:
- (Implicit) Fix the exec unnecessary implicit fencing (Matt Brost)

Driver Changes:
- Fix an inverted if statement (Colin)
- Fixes around display d3cold vs non-d3cold runtime pm (Imre)
- A couple of scheduling fixes (Matt Brost)
- Increase a query timestamp witdh (Lucas)
- Move a timestamp read (Lucas)
- Tidy some code using multiple put_user() (Lucas)
- Fix an ufence signaling error (Nirmoy)
- Initialize the ufence.signalled field (Matt Auld)
- Display fb alignement work (Juha-Pekka)
- Disallow horisontal flip with tile4 + display20 (Juha-Pekka)
- Extend a workaround (Shekhar)
- Enlarge the global invalidation timeout (Shuicheng)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Thomas Hellstrom <thomas.hellstrom@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZxDZaRRQAzrG1uir@fedora
This commit is contained in:
Dave Airlie 2024-10-18 15:17:50 +10:00
commit 0a4d0b2d9d
19 changed files with 147 additions and 78 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/drm/i915/display/intel_fb.c
View File

@ -519,6 +519,19 @@ bool intel_fb_needs_64k_phys(u64 modifier)
INTEL_PLANE_CAP_NEED64K_PHYS);
}
/**
* intel_fb_is_tile4_modifier: Check if a modifier is a tile4 modifier type
* @modifier: Modifier to check
*
* Returns:
* Returns %true if @modifier is a tile4 modifier.
*/
bool intel_fb_is_tile4_modifier(u64 modifier)
{
return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
INTEL_PLANE_CAP_TILING_4);
}
static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
u8 display_ver_from, u8 display_ver_until)
{

1
drivers/gpu/drm/i915/display/intel_fb.h
View File

@ -36,6 +36,7 @@ bool intel_fb_is_ccs_modifier(u64 modifier);
bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
bool intel_fb_is_mc_ccs_modifier(u64 modifier);
bool intel_fb_needs_64k_phys(u64 modifier);
bool intel_fb_is_tile4_modifier(u64 modifier);
bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);

11
drivers/gpu/drm/i915/display/skl_universal_plane.c
View File

@ -1618,6 +1618,17 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
return -EINVAL;
}
/*
* Display20 onward tile4 hflip is not supported
*/
if (rotation & DRM_MODE_REFLECT_X &&
intel_fb_is_tile4_modifier(fb->modifier) &&
DISPLAY_VER(dev_priv) >= 20) {
drm_dbg_kms(&dev_priv->drm,
"horizontal flip is not supported with tile4 surface formats\n");
return -EINVAL;
}
if (drm_rotation_90_or_270(rotation)) {
if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) {
drm_dbg_kms(&dev_priv->drm,

2
drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_stolen.h
View File

@ -29,7 +29,7 @@ static inline int i915_gem_stolen_insert_node_in_range(struct xe_device *xe,
bo = xe_bo_create_locked_range(xe, xe_device_get_root_tile(xe),
NULL, size, start, end,
ttm_bo_type_kernel, flags);
ttm_bo_type_kernel, flags, 0);
if (IS_ERR(bo)) {
err = PTR_ERR(bo);
bo = NULL;

20
drivers/gpu/drm/xe/display/xe_display.c
View File

@ -345,6 +345,9 @@ static void __xe_display_pm_suspend(struct xe_device *xe, bool runtime)
intel_opregion_suspend(display, s2idle ? PCI_D1 : PCI_D3cold);
intel_dmc_suspend(display);
if (runtime && has_display(xe))
intel_hpd_poll_enable(xe);
}
void xe_display_pm_suspend(struct xe_device *xe)
@ -387,8 +390,10 @@ void xe_display_pm_runtime_suspend(struct xe_device *xe)
if (!xe->info.probe_display)
return;
if (xe->d3cold.allowed)
if (xe->d3cold.allowed) {
__xe_display_pm_suspend(xe, true);
return;
}
intel_hpd_poll_enable(xe);
}
@ -453,9 +458,11 @@ static void __xe_display_pm_resume(struct xe_device *xe, bool runtime)
intel_display_driver_resume(xe);
drm_kms_helper_poll_enable(&xe->drm);
intel_display_driver_enable_user_access(xe);
intel_hpd_poll_disable(xe);
}
if (has_display(xe))
intel_hpd_poll_disable(xe);
intel_opregion_resume(display);
if (!runtime)
@ -474,10 +481,13 @@ void xe_display_pm_runtime_resume(struct xe_device *xe)
if (!xe->info.probe_display)
return;
intel_hpd_poll_disable(xe);
if (xe->d3cold.allowed)
if (xe->d3cold.allowed) {
__xe_display_pm_resume(xe, true);
return;
}
intel_hpd_init(xe);
intel_hpd_poll_disable(xe);
}

57
drivers/gpu/drm/xe/display/xe_fb_pin.c
View File

@ -79,7 +79,8 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs,
static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
const struct i915_gtt_view *view,
struct i915_vma *vma)
struct i915_vma *vma,
u64 physical_alignment)
{
struct xe_device *xe = to_xe_device(fb->base.dev);
struct xe_tile *tile0 = xe_device_get_root_tile(xe);
@ -99,23 +100,29 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
XE_PAGE_SIZE);
if (IS_DGFX(xe))
dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
ttm_bo_type_kernel,
XE_BO_FLAG_VRAM0 |
XE_BO_FLAG_GGTT |
XE_BO_FLAG_PAGETABLE);
dpt = xe_bo_create_pin_map_at_aligned(xe, tile0, NULL,
dpt_size, ~0ull,
ttm_bo_type_kernel,
XE_BO_FLAG_VRAM0 |
XE_BO_FLAG_GGTT |
XE_BO_FLAG_PAGETABLE,
physical_alignment);
else
dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
ttm_bo_type_kernel,
XE_BO_FLAG_STOLEN |
XE_BO_FLAG_GGTT |
XE_BO_FLAG_PAGETABLE);
dpt = xe_bo_create_pin_map_at_aligned(xe, tile0, NULL,
dpt_size, ~0ull,
ttm_bo_type_kernel,
XE_BO_FLAG_STOLEN |
XE_BO_FLAG_GGTT |
XE_BO_FLAG_PAGETABLE,
physical_alignment);
if (IS_ERR(dpt))
dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
ttm_bo_type_kernel,
XE_BO_FLAG_SYSTEM |
XE_BO_FLAG_GGTT |
XE_BO_FLAG_PAGETABLE);
dpt = xe_bo_create_pin_map_at_aligned(xe, tile0, NULL,
dpt_size, ~0ull,
ttm_bo_type_kernel,
XE_BO_FLAG_SYSTEM |
XE_BO_FLAG_GGTT |
XE_BO_FLAG_PAGETABLE,
physical_alignment);
if (IS_ERR(dpt))
return PTR_ERR(dpt);
@ -184,7 +191,8 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt, u32 *ggtt_ofs, u32 bo
static int __xe_pin_fb_vma_ggtt(const struct intel_framebuffer *fb,
const struct i915_gtt_view *view,
struct i915_vma *vma)
struct i915_vma *vma,
u64 physical_alignment)
{
struct drm_gem_object *obj = intel_fb_bo(&fb->base);
struct xe_bo *bo = gem_to_xe_bo(obj);
@ -266,7 +274,8 @@ static int __xe_pin_fb_vma_ggtt(const struct intel_framebuffer *fb,
}
static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
const struct i915_gtt_view *view)
const struct i915_gtt_view *view,
u64 physical_alignment)
{
struct drm_device *dev = fb->base.dev;
struct xe_device *xe = to_xe_device(dev);
@ -315,9 +324,9 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
vma->bo = bo;
if (intel_fb_uses_dpt(&fb->base))
ret = __xe_pin_fb_vma_dpt(fb, view, vma);
ret = __xe_pin_fb_vma_dpt(fb, view, vma, physical_alignment);
else
ret = __xe_pin_fb_vma_ggtt(fb, view, vma);
ret = __xe_pin_fb_vma_ggtt(fb, view, vma, physical_alignment);
if (ret)
goto err_unpin;
@ -358,7 +367,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
{
*out_flags = 0;
return __xe_pin_fb_vma(to_intel_framebuffer(fb), view);
return __xe_pin_fb_vma(to_intel_framebuffer(fb), view, phys_alignment);
}
void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags)
@ -372,11 +381,15 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
struct drm_gem_object *obj = intel_fb_bo(fb);
struct xe_bo *bo = gem_to_xe_bo(obj);
struct i915_vma *vma;
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
u64 phys_alignment = plane->min_alignment(plane, fb, 0);
/* We reject creating !SCANOUT fb's, so this is weird.. */
drm_WARN_ON(bo->ttm.base.dev, !(bo->flags & XE_BO_FLAG_SCANOUT));
vma = __xe_pin_fb_vma(to_intel_framebuffer(fb), &plane_state->view.gtt);
vma = __xe_pin_fb_vma(intel_fb, &plane_state->view.gtt, phys_alignment);
if (IS_ERR(vma))
return PTR_ERR(vma);

29
drivers/gpu/drm/xe/xe_bo.c
View File

@ -1454,7 +1454,8 @@ static struct xe_bo *
__xe_bo_create_locked(struct xe_device *xe,
struct xe_tile *tile, struct xe_vm *vm,
size_t size, u64 start, u64 end,
u16 cpu_caching, enum ttm_bo_type type, u32 flags)
u16 cpu_caching, enum ttm_bo_type type, u32 flags,
u64 alignment)
{
struct xe_bo *bo = NULL;
int err;
@ -1483,6 +1484,8 @@ __xe_bo_create_locked(struct xe_device *xe,
if (IS_ERR(bo))
return bo;
bo->min_align = alignment;
/*
* Note that instead of taking a reference no the drm_gpuvm_resv_bo(),
* to ensure the shared resv doesn't disappear under the bo, the bo
@ -1523,16 +1526,18 @@ struct xe_bo *
xe_bo_create_locked_range(struct xe_device *xe,
struct xe_tile *tile, struct xe_vm *vm,
size_t size, u64 start, u64 end,
enum ttm_bo_type type, u32 flags)
enum ttm_bo_type type, u32 flags, u64 alignment)
{
return __xe_bo_create_locked(xe, tile, vm, size, start, end, 0, type, flags);
return __xe_bo_create_locked(xe, tile, vm, size, start, end, 0, type,
flags, alignment);
}
struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size,
enum ttm_bo_type type, u32 flags)
{
return __xe_bo_create_locked(xe, tile, vm, size, 0, ~0ULL, 0, type, flags);
return __xe_bo_create_locked(xe, tile, vm, size, 0, ~0ULL, 0, type,
flags, 0);
}
struct xe_bo *xe_bo_create_user(struct xe_device *xe, struct xe_tile *tile,
@ -1542,7 +1547,7 @@ struct xe_bo *xe_bo_create_user(struct xe_device *xe, struct xe_tile *tile,
{
struct xe_bo *bo = __xe_bo_create_locked(xe, tile, vm, size, 0, ~0ULL,
cpu_caching, ttm_bo_type_device,
flags | XE_BO_FLAG_USER);
flags | XE_BO_FLAG_USER, 0);
if (!IS_ERR(bo))
xe_bo_unlock_vm_held(bo);
@ -1565,6 +1570,17 @@ struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_tile *tile
struct xe_vm *vm,
size_t size, u64 offset,
enum ttm_bo_type type, u32 flags)
{
return xe_bo_create_pin_map_at_aligned(xe, tile, vm, size, offset,
type, flags, 0);
}
struct xe_bo *xe_bo_create_pin_map_at_aligned(struct xe_device *xe,
struct xe_tile *tile,
struct xe_vm *vm,
size_t size, u64 offset,
enum ttm_bo_type type, u32 flags,
u64 alignment)
{
struct xe_bo *bo;
int err;
@ -1576,7 +1592,8 @@ struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_tile *tile
flags |= XE_BO_FLAG_GGTT;
bo = xe_bo_create_locked_range(xe, tile, vm, size, start, end, type,
flags | XE_BO_FLAG_NEEDS_CPU_ACCESS);
flags | XE_BO_FLAG_NEEDS_CPU_ACCESS,
alignment);
if (IS_ERR(bo))
return bo;

8
drivers/gpu/drm/xe/xe_bo.h
View File

@ -77,7 +77,7 @@ struct xe_bo *
xe_bo_create_locked_range(struct xe_device *xe,
struct xe_tile *tile, struct xe_vm *vm,
size_t size, u64 start, u64 end,
enum ttm_bo_type type, u32 flags);
enum ttm_bo_type type, u32 flags, u64 alignment);
struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size,
enum ttm_bo_type type, u32 flags);
@ -94,6 +94,12 @@ struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,
struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size, u64 offset,
enum ttm_bo_type type, u32 flags);
struct xe_bo *xe_bo_create_pin_map_at_aligned(struct xe_device *xe,
struct xe_tile *tile,
struct xe_vm *vm,
size_t size, u64 offset,
enum ttm_bo_type type, u32 flags,
u64 alignment);
struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,
const void *data, size_t size,
enum ttm_bo_type type, u32 flags);

5
drivers/gpu/drm/xe/xe_bo_types.h
View File

@ -76,6 +76,11 @@ struct xe_bo {
/** @vram_userfault_link: Link into @mem_access.vram_userfault.list */
struct list_head vram_userfault_link;
/** @min_align: minimum alignment needed for this BO if different
* from default
*/
u64 min_align;
};
#endif

2
drivers/gpu/drm/xe/xe_device.c
View File

@ -925,7 +925,7 @@ void xe_device_l2_flush(struct xe_device *xe)
spin_lock(&gt->global_invl_lock);
xe_mmio_write32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1);
if (xe_mmio_wait32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 150, NULL, true))
if (xe_mmio_wait32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 500, NULL, true))
xe_gt_err_once(gt, "Global invalidation timeout\n");
spin_unlock(&gt->global_invl_lock);

12
drivers/gpu/drm/xe/xe_exec.c
View File

@ -41,11 +41,6 @@
* user knows an exec writes to a BO and reads from the BO in the next exec, it
* is the user's responsibility to pass in / out fence between the two execs).
*
* Implicit dependencies for external BOs are handled by using the dma-buf
* implicit dependency uAPI (TODO: add link). To make this works each exec must
* install the job's fence into the DMA_RESV_USAGE_WRITE slot of every external
* BO mapped in the VM.
*
* We do not allow a user to trigger a bind at exec time rather we have a VM
* bind IOCTL which uses the same in / out fence interface as exec. In that
* sense, a VM bind is basically the same operation as an exec from the user
@ -59,8 +54,8 @@
* behind any pending kernel operations on any external BOs in VM or any BOs
* private to the VM. This is accomplished by the rebinds waiting on BOs
* DMA_RESV_USAGE_KERNEL slot (kernel ops) and kernel ops waiting on all BOs
* slots (inflight execs are in the DMA_RESV_USAGE_BOOKING for private BOs and
* in DMA_RESV_USAGE_WRITE for external BOs).
* slots (inflight execs are in the DMA_RESV_USAGE_BOOKKEEP for private BOs and
* for external BOs).
*
* Rebinds / dma-resv usage applies to non-compute mode VMs only as for compute
* mode VMs we use preempt fences and a rebind worker (TODO: add link).
@ -304,7 +299,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
xe_sched_job_arm(job);
if (!xe_vm_in_lr_mode(vm))
drm_gpuvm_resv_add_fence(&vm->gpuvm, exec, &job->drm.s_fence->finished,
DMA_RESV_USAGE_BOOKKEEP, DMA_RESV_USAGE_WRITE);
DMA_RESV_USAGE_BOOKKEEP,
DMA_RESV_USAGE_BOOKKEEP);
for (i = 0; i < num_syncs; i++) {
xe_sync_entry_signal(&syncs[i], &job->drm.s_fence->finished);

2
drivers/gpu/drm/xe/xe_ggtt.c
View File

@ -603,7 +603,7 @@ static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,
u64 start, u64 end)
{
int err;
u64 alignment = XE_PAGE_SIZE;
u64 alignment = bo->min_align > 0 ? bo->min_align : XE_PAGE_SIZE;
if (xe_bo_is_vram(bo) && ggtt->flags & XE_GGTT_FLAGS_64K)
alignment = SZ_64K;

2
drivers/gpu/drm/xe/xe_gpu_scheduler.h
View File

@ -63,7 +63,9 @@ xe_sched_invalidate_job(struct xe_sched_job *job, int threshold)
static inline void xe_sched_add_pending_job(struct xe_gpu_scheduler *sched,
struct xe_sched_job *job)
{
spin_lock(&sched->base.job_list_lock);
list_add(&job->drm.list, &sched->base.pending_list);
spin_unlock(&sched->base.job_list_lock);
}
static inline

2
drivers/gpu/drm/xe/xe_guc_log.c
View File

@ -122,7 +122,7 @@ void xe_guc_log_snapshot_free(struct xe_guc_log_snapshot *snapshot)
if (!snapshot)
return;
if (!snapshot->copy) {
if (snapshot->copy) {
for (i = 0; i < snapshot->num_chunks; i++)
kfree(snapshot->copy[i]);
kfree(snapshot->copy);

7
drivers/gpu/drm/xe/xe_guc_submit.c
View File

@ -1105,10 +1105,13 @@ guc_exec_queue_timedout_job(struct drm_sched_job *drm_job)
/*
* TDR has fired before free job worker. Common if exec queue
* immediately closed after last fence signaled.
* immediately closed after last fence signaled. Add back to pending
* list so job can be freed and kick scheduler ensuring free job is not
* lost.
*/
if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &job->fence->flags)) {
guc_exec_queue_free_job(drm_job);
xe_sched_add_pending_job(sched, job);
xe_sched_submission_start(sched);
return DRM_GPU_SCHED_STAT_NOMINAL;
}

42
drivers/gpu/drm/xe/xe_query.c
View File

@ -85,16 +85,13 @@ static __ktime_func_t __clock_id_to_func(clockid_t clk_id)
}
static void
__read_timestamps(struct xe_gt *gt,
struct xe_reg lower_reg,
struct xe_reg upper_reg,
u64 *engine_ts,
u64 *cpu_ts,
u64 *cpu_delta,
__ktime_func_t cpu_clock)
hwe_read_timestamp(struct xe_hw_engine *hwe, u64 *engine_ts, u64 *cpu_ts,
u64 *cpu_delta, __ktime_func_t cpu_clock)
{
struct xe_mmio *mmio = &gt->mmio;
struct xe_mmio *mmio = &hwe->gt->mmio;
u32 upper, lower, old_upper, loop = 0;
struct xe_reg upper_reg = RING_TIMESTAMP_UDW(hwe->mmio_base),
lower_reg = RING_TIMESTAMP(hwe->mmio_base);
upper = xe_mmio_read32(mmio, upper_reg);
do {
@ -155,28 +152,21 @@ query_engine_cycles(struct xe_device *xe,
if (xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL))
return -EIO;
__read_timestamps(gt,
RING_TIMESTAMP(hwe->mmio_base),
RING_TIMESTAMP_UDW(hwe->mmio_base),
&resp.engine_cycles,
&resp.cpu_timestamp,
&resp.cpu_delta,
cpu_clock);
hwe_read_timestamp(hwe, &resp.engine_cycles, &resp.cpu_timestamp,
&resp.cpu_delta, cpu_clock);
xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
resp.width = 36;
if (GRAPHICS_VER(xe) >= 20)
resp.width = 64;
else
resp.width = 36;
/* Only write to the output fields of user query */
if (put_user(resp.cpu_timestamp, &query_ptr->cpu_timestamp))
return -EFAULT;
if (put_user(resp.cpu_delta, &query_ptr->cpu_delta))
return -EFAULT;
if (put_user(resp.engine_cycles, &query_ptr->engine_cycles))
return -EFAULT;
if (put_user(resp.width, &query_ptr->width))
if (put_user(resp.cpu_timestamp, &query_ptr->cpu_timestamp) ||
put_user(resp.cpu_delta, &query_ptr->cpu_delta) ||
put_user(resp.engine_cycles, &query_ptr->engine_cycles) ||
put_user(resp.width, &query_ptr->width))
return -EFAULT;
return 0;

2
drivers/gpu/drm/xe/xe_sync.c
View File

@ -58,7 +58,7 @@ static struct xe_user_fence *user_fence_create(struct xe_device *xe, u64 addr,
if (!access_ok(ptr, sizeof(*ptr)))
return ERR_PTR(-EFAULT);
ufence = kmalloc(sizeof(*ufence), GFP_KERNEL);
ufence = kzalloc(sizeof(*ufence), GFP_KERNEL);
if (!ufence)
return ERR_PTR(-ENOMEM);

5
drivers/gpu/drm/xe/xe_wa.c
View File

@ -602,6 +602,11 @@ static const struct xe_rtp_entry_sr engine_was[] = {
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
},
{ XE_RTP_NAME("18034896535"),
XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
},
{}
};

3
drivers/gpu/drm/xe/xe_wait_user_fence.c
View File

@ -169,9 +169,6 @@ int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data,
args->timeout = 0;
}
if (!timeout && !(err < 0))
err = -ETIME;
if (q)
xe_exec_queue_put(q);