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drm/i915: Disable RPG during live selftest
The Forcewake timeout issue has been observed on Gen 12.0 and above.
To address this, disable Render Power-Gating (RPG) during live self-tests
for these generations. The temporary workaround 'drm/i915/mtl: do not
enable render power-gating on MTL' disables RPG globally, which is
unnecessary since the issues were only seen during self-tests.
v2: take runtime pm wakeref
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413
Fixes: 25e7976db8 ("drm/i915/mtl: do not enable render power-gating on MTL")
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Sk Anirban <sk.anirban@intel.com>
Reviewed-by: Karthik Poosa <karthik.poosa@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250310152821.2931678-1-sk.anirban@intel.com
This commit is contained in:
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@ -117,21 +117,10 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
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GEN6_RC_CTL_RC6_ENABLE |
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GEN6_RC_CTL_EI_MODE(1);
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/*
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* BSpec 52698 - Render powergating must be off.
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* FIXME BSpec is outdated, disabling powergating for MTL is just
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* temporary wa and should be removed after fixing real cause
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* of forcewake timeouts.
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*/
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if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
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pg_enable =
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GEN9_MEDIA_PG_ENABLE |
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GEN11_MEDIA_SAMPLER_PG_ENABLE;
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else
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pg_enable =
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GEN9_RENDER_PG_ENABLE |
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GEN9_MEDIA_PG_ENABLE |
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GEN11_MEDIA_SAMPLER_PG_ENABLE;
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pg_enable =
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GEN9_RENDER_PG_ENABLE |
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GEN9_MEDIA_PG_ENABLE |
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GEN11_MEDIA_SAMPLER_PG_ENABLE;
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if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {
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for (i = 0; i < I915_MAX_VCS; i++)
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@ -23,7 +23,9 @@
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#include <linux/random.h>
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#include "gt/intel_gt.h"
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#include "gt/intel_gt_pm.h"
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#include "gt/intel_gt_regs.h"
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#include "gt/uc/intel_gsc_fw.h"
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#include "i915_driver.h"
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@ -253,11 +255,27 @@ int i915_mock_selftests(void)
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int i915_live_selftests(struct pci_dev *pdev)
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{
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struct drm_i915_private *i915 = pdev_to_i915(pdev);
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struct intel_uncore *uncore = &i915->uncore;
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int err;
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u32 pg_enable;
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intel_wakeref_t wakeref;
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if (!i915_selftest.live)
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return 0;
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/*
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* FIXME Disable render powergating, this is temporary wa and should be removed
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* after fixing real cause of forcewake timeouts.
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*/
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with_intel_runtime_pm(uncore->rpm, wakeref) {
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if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 00), IP_VER(12, 74))) {
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pg_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
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if (pg_enable & GEN9_RENDER_PG_ENABLE)
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intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
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pg_enable & ~GEN9_RENDER_PG_ENABLE);
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}
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}
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__wait_gsc_proxy_completed(i915);
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__wait_gsc_huc_load_completed(i915);
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