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drm/xe/xe2: Program GuC's MOCS on Xe2 and beyond

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As with PVC, Xe2 platforms require that the index of an uncached MOCS
entry be programmed into the GUC_SHIM_CONTROL register.  This will
likely be needed on future platforms as well.

Xe2 also extends the size of the MOCS index register field from two bits
to four bits.  Since these extra bits were unused on PVC, it should be
safe to just increase the size of the mask.

Bspec: 60592
Cc: Haridhar Kalvala <haridhar.kalvala@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-08-11 09:06:15 -07:00 committed by Rodrigo Vivi
parent e4751ab5d2
commit 0993b22f93
2 changed files with 2 additions and 2 deletions
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2
drivers/gpu/drm/xe/regs/xe_guc_regs.h
View File

@ -45,7 +45,7 @@
#define GUC_WOPCM_SIZE_LOCKED REG_BIT(0)
#define GUC_SHIM_CONTROL XE_REG(0xc064)
#define GUC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
#define GUC_MOCS_INDEX_MASK REG_GENMASK(27, 24)
#define GUC_SHIM_WC_ENABLE REG_BIT(21)
#define GUC_ENABLE_MIA_CLOCK_GATING REG_BIT(15)
#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA REG_BIT(10)

2
drivers/gpu/drm/xe/xe_guc.c
View File

@ -326,7 +326,7 @@ static void guc_prepare_xfer(struct xe_guc *guc)
shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
GUC_ENABLE_MIA_CACHING;
if (xe->info.platform == XE_PVC)
if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC)
shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index);
/* Must program this register before loading the ucode with DMA */