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drm/amd/display: Add DCC/Tiling reset helper for DCN and DCE

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This commit introduces a function helper for resetting DCN/DCE DCC and
tiling. Those functions are generic for their respective DCN/DCE, so
they were added to the oldest version of each architecture.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira 2025-02-04 08:07:21 -07:00 committed by Alex Deucher
parent 8ae6dfc0b6
commit 098c9b58be
4 changed files with 66 additions and 0 deletions
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29
drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
View File

@ -140,3 +140,32 @@ void dce100_hw_sequencer_construct(struct dc *dc)
dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
}
/**
* dce100_reset_surface_dcc_and_tiling - Set DCC and tiling in DCE to their disable mode.
*
* @pipe_ctx: Pointer to the pipe context structure.
* @plane_state: Surface state
* @clear_tiling: If true set tiling to Linear, otherwise does not change tiling
*
* This function is responsible for call the HUBP block to disable DCC and set
* tiling to the linear mode.
*/
void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,
struct dc_plane_state *plane_state,
bool clear_tiling)
{
struct mem_input *mi = pipe_ctx->plane_res.mi;
if (!mi)
return;
/* if framebuffer is tiled, disable tiling */
if (clear_tiling && mi->funcs->mem_input_clear_tiling)
mi->funcs->mem_input_clear_tiling(mi);
/* force page flip to see the new content of the framebuffer */
mi->funcs->mem_input_program_surface_flip_and_addr(mi,
&plane_state->address,
true);
}

4
drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h
View File

@ -46,5 +46,9 @@ bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
struct dc_bios *dcb,
enum pipe_gating_control power_gating);
void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,
struct dc_plane_state *plane_state,
bool clear_tiling);
#endif /* __DC_HWSS_DCE100_H__ */

29
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
View File

@ -3920,3 +3920,32 @@ void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits)
dcc_en_bits[i] = s->dcc_en ? 1 : 0;
}
}
/**
* dcn10_reset_surface_dcc_and_tiling - Set DCC and tiling in DCN to their disable mode.
*
* @pipe_ctx: Pointer to the pipe context structure.
* @plane_state: Surface state
* @clear_tiling: If true set tiling to Linear, otherwise does not change tiling
*
* This function is responsible for call the HUBP block to disable DCC and set
* tiling to the linear mode.
*/
void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,
struct dc_plane_state *plane_state,
bool clear_tiling)
{
struct hubp *hubp = pipe_ctx->plane_res.hubp;
if (!hubp)
return;
/* if framebuffer is tiled, disable tiling */
if (clear_tiling && hubp->funcs->hubp_clear_tiling)
hubp->funcs->hubp_clear_tiling(hubp);
/* force page flip to see the new content of the framebuffer */
hubp->funcs->hubp_program_surface_flip_and_addr(hubp,
&plane_state->address,
true);
}

4
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
View File

@ -207,4 +207,8 @@ void dcn10_update_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
int mpcc_id);
void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,
struct dc_plane_state *plane_state,
bool clear_tiling);
#endif /* __DC_HWSS_DCN10_H__ */