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drm/amdgpu/gfx12: add support for disable_kq
Plumb in support for disabling kernel queues. v2: use ring counts per Felix' suggestion v3: fix stream fault handler, enable EOP interrupts v4: fix MEC interrupt offset (Sunil) v5: clean up after removing extra sched.ready settings Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
1e63ebc0d4
commit
0981e0ef18
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@ -1442,11 +1442,13 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
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break;
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}
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/* recalculate compute rings to use based on hardware configuration */
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num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
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adev->gfx.mec.num_queue_per_pipe) / 2;
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adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
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num_compute_rings);
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if (adev->gfx.num_compute_rings) {
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/* recalculate compute rings to use based on hardware configuration */
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num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
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adev->gfx.mec.num_queue_per_pipe) / 2;
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adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
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num_compute_rings);
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}
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/* EOP Event */
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r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
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@ -1492,37 +1494,41 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
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return r;
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}
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/* set up the gfx ring */
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for (i = 0; i < adev->gfx.me.num_me; i++) {
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for (j = 0; j < num_queue_per_pipe; j++) {
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for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
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if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
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continue;
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if (adev->gfx.num_gfx_rings) {
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/* set up the gfx ring */
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for (i = 0; i < adev->gfx.me.num_me; i++) {
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for (j = 0; j < num_queue_per_pipe; j++) {
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for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
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if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
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continue;
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r = gfx_v12_0_gfx_ring_init(adev, ring_id,
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i, k, j);
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if (r)
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return r;
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ring_id++;
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r = gfx_v12_0_gfx_ring_init(adev, ring_id,
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i, k, j);
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if (r)
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return r;
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ring_id++;
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}
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}
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}
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}
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ring_id = 0;
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/* set up the compute queues - allocate horizontally across pipes */
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for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
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for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
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for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
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if (!amdgpu_gfx_is_mec_queue_enabled(adev,
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0, i, k, j))
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continue;
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if (adev->gfx.num_compute_rings) {
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ring_id = 0;
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/* set up the compute queues - allocate horizontally across pipes */
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for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
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for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
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for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
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if (!amdgpu_gfx_is_mec_queue_enabled(adev,
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0, i, k, j))
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continue;
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r = gfx_v12_0_compute_ring_init(adev, ring_id,
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i, k, j);
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if (r)
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return r;
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r = gfx_v12_0_compute_ring_init(adev, ring_id,
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i, k, j);
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if (r)
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return r;
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ring_id++;
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ring_id++;
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}
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}
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}
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}
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@ -3671,6 +3677,46 @@ static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
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return r;
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}
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static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
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bool enable)
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{
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if (adev->gfx.disable_kq) {
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unsigned int irq_type;
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int m, p, r;
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for (m = 0; m < adev->gfx.me.num_me; m++) {
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for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
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irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
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if (enable)
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r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
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irq_type);
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else
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r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
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irq_type);
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if (r)
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return r;
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}
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}
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for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
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for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
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irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
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+ (m * adev->gfx.mec.num_pipe_per_mec)
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+ p;
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if (enable)
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r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
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irq_type);
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else
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r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
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irq_type);
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if (r)
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return r;
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}
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}
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}
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return 0;
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}
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static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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@ -3681,6 +3727,7 @@ static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
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amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
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gfx_v12_0_set_userq_eop_interrupts(adev, false);
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if (!adev->no_hw_access) {
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if (amdgpu_async_gfx_ring) {
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@ -3769,11 +3816,19 @@ static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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if (amdgpu_disable_kq == 1)
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adev->gfx.disable_kq = true;
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adev->gfx.funcs = &gfx_v12_0_gfx_funcs;
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adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
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adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
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AMDGPU_MAX_COMPUTE_RINGS);
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if (adev->gfx.disable_kq) {
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adev->gfx.num_gfx_rings = 0;
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adev->gfx.num_compute_rings = 0;
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} else {
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adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
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adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
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AMDGPU_MAX_COMPUTE_RINGS);
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}
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gfx_v12_0_set_kiq_pm4_funcs(adev);
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gfx_v12_0_set_ring_funcs(adev);
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@ -3804,6 +3859,10 @@ static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block)
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if (r)
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return r;
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r = gfx_v12_0_set_userq_eop_interrupts(adev, true);
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if (r)
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return r;
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return 0;
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}
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@ -4935,27 +4994,29 @@ static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev,
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pipe_id = (entry->ring_id & 0x03) >> 0;
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queue_id = (entry->ring_id & 0x70) >> 4;
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switch (me_id) {
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case 0:
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for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
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ring = &adev->gfx.gfx_ring[i];
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if (ring->me == me_id && ring->pipe == pipe_id &&
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ring->queue == queue_id)
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drm_sched_fault(&ring->sched);
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if (!adev->gfx.disable_kq) {
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switch (me_id) {
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case 0:
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for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
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ring = &adev->gfx.gfx_ring[i];
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if (ring->me == me_id && ring->pipe == pipe_id &&
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ring->queue == queue_id)
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drm_sched_fault(&ring->sched);
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}
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break;
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case 1:
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case 2:
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for (i = 0; i < adev->gfx.num_compute_rings; i++) {
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ring = &adev->gfx.compute_ring[i];
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if (ring->me == me_id && ring->pipe == pipe_id &&
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ring->queue == queue_id)
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drm_sched_fault(&ring->sched);
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}
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break;
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default:
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BUG();
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break;
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}
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break;
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case 1:
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case 2:
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for (i = 0; i < adev->gfx.num_compute_rings; i++) {
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ring = &adev->gfx.compute_ring[i];
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if (ring->me == me_id && ring->pipe == pipe_id &&
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ring->queue == queue_id)
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drm_sched_fault(&ring->sched);
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}
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break;
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default:
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BUG();
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break;
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}
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}
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