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arm64: dts: ti: k3-j784s4-j742s2-main-common: Add DSI & DSI PHY

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Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge
is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Tested-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250716060114.52122-2-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Jayesh Choudhary 2025-07-16 11:31:08 +05:30 committed by Nishanth Menon
parent 8f5ae30d69
commit 09449e48be
1 changed files with 39 additions and 0 deletions
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39
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
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@ -2522,6 +2522,45 @@ watchdog18: watchdog@2550000 {
status = "reserved";
};
dphy_tx0: phy@4480000 {
compatible = "ti,j721e-dphy";
reg = <0x00 0x04480000 0x00 0x00001000>;
clocks = <&k3_clks 402 20>, <&k3_clks 402 3>;
clock-names = "psm", "pll_ref";
#phy-cells = <0>;
power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 402 3>;
assigned-clock-parents = <&k3_clks 402 4>;
assigned-clock-rates = <19200000>;
status = "disabled";
};
dsi0: dsi@4800000 {
compatible = "ti,j721e-dsi";
reg = <0x00 0x04800000 0x00 0x00100000>,
<0x00 0x04710000 0x00 0x00000100>;
clocks = <&k3_clks 215 2>, <&k3_clks 215 5>;
clock-names = "dsi_p_clk", "dsi_sys_clk";
power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
phys = <&dphy_tx0>;
phy-names = "dphy";
status = "disabled";
dsi0_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
};
};
mhdp: bridge@a000000 {
compatible = "ti,j721e-mhdp8546";
reg = <0x0 0xa000000 0x0 0x30a00>,