github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-08 22:52:35 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

clk: rockchip: rk3328: Fix clk_cif_src parent

Browse Source 
Change-Id: I0ea209224880b8c51a385ed46827bb0d8f7dd219
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2018-02-08 19:18:52 +08:00 committed by Tao Huang
parent 0cb664eb76
commit 093bfc848c
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/rockchip/clk-rk3328.c
View File

@ -148,7 +148,7 @@ static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = {
};
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_hdmiphy_gpll_p) = { "hdmiphy", "gpll" };
PNAME(mux_2plls_p) = { "cpll", "gpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
@ -592,7 +592,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
GATE(SCLK_HDMI_SFC, "clk_hdmi_sfc", "xin24m", 0,
RK3328_CLKGATE_CON(5), 4, GFLAGS),
COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
COMPOSITE_NODIV(0, "clk_cif_src", mux_hdmiphy_gpll_p, 0,
RK3328_CLKSEL_CON(42), 7, 1, MFLAGS,
RK3328_CLKGATE_CON(5), 3, GFLAGS),
COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT,