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drm/amdgpu: add defines for pin_offsets in DCE8
Define pin_offsets values in the same way it is done in DCE8 Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -51,6 +51,15 @@
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#define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
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#define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
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/* audio endpt instance offsets */
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#define AUD0_REGISTER_OFFSET (0x1780 - 0x1780)
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#define AUD1_REGISTER_OFFSET (0x1786 - 0x1780)
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#define AUD2_REGISTER_OFFSET (0x178c - 0x1780)
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#define AUD3_REGISTER_OFFSET (0x1792 - 0x1780)
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#define AUD4_REGISTER_OFFSET (0x1798 - 0x1780)
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#define AUD5_REGISTER_OFFSET (0x179d - 0x1780)
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#define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780)
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#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
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#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
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@ -1395,13 +1395,13 @@ static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
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}
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static const u32 pin_offsets[7] = {
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(0x1780 - 0x1780),
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(0x1786 - 0x1780),
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(0x178c - 0x1780),
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(0x1792 - 0x1780),
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(0x1798 - 0x1780),
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(0x179d - 0x1780),
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(0x17a4 - 0x1780),
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AUD0_REGISTER_OFFSET,
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AUD1_REGISTER_OFFSET,
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AUD2_REGISTER_OFFSET,
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AUD3_REGISTER_OFFSET,
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AUD4_REGISTER_OFFSET,
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AUD5_REGISTER_OFFSET,
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AUD6_REGISTER_OFFSET,
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};
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static int dce_v8_0_audio_init(struct amdgpu_device *adev)
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