drm/amdgpu: add defines for pin_offsets in DCE8

Define pin_offsets values in the same way it is done in DCE8

Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alexandre Demers 2025-03-05 20:49:56 -05:00 committed by Alex Deucher
parent 9c551ca3db
commit 092da9fb25
2 changed files with 16 additions and 7 deletions

View File

@ -51,6 +51,15 @@
#define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
#define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
/* audio endpt instance offsets */
#define AUD0_REGISTER_OFFSET (0x1780 - 0x1780)
#define AUD1_REGISTER_OFFSET (0x1786 - 0x1780)
#define AUD2_REGISTER_OFFSET (0x178c - 0x1780)
#define AUD3_REGISTER_OFFSET (0x1792 - 0x1780)
#define AUD4_REGISTER_OFFSET (0x1798 - 0x1780)
#define AUD5_REGISTER_OFFSET (0x179d - 0x1780)
#define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780)
#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003

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@ -1395,13 +1395,13 @@ static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
}
static const u32 pin_offsets[7] = {
(0x1780 - 0x1780),
(0x1786 - 0x1780),
(0x178c - 0x1780),
(0x1792 - 0x1780),
(0x1798 - 0x1780),
(0x179d - 0x1780),
(0x17a4 - 0x1780),
AUD0_REGISTER_OFFSET,
AUD1_REGISTER_OFFSET,
AUD2_REGISTER_OFFSET,
AUD3_REGISTER_OFFSET,
AUD4_REGISTER_OFFSET,
AUD5_REGISTER_OFFSET,
AUD6_REGISTER_OFFSET,
};
static int dce_v8_0_audio_init(struct amdgpu_device *adev)