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drm/amdgpu: Add a new NPA Address space

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Add a new address space for NPA address management.
This is needed for sharing buffer objects across GPUs
with each running their own OS. The NPA address space
size can change across different HW generations so the
size is initialized during early init of the driver boot
up process.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mukul Joshi 2026-04-27 19:09:45 -04:00 committed by Alex Deucher
parent 742beddd51
commit 09152b002f
8 changed files with 45 additions and 3 deletions
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11
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
View File

@ -204,6 +204,14 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
c++;
}
if (domain & AMDGPU_GEM_DOMAIN_NPA) {
places[c].fpfn = 0;
places[c].lpfn = 0;
places[c].mem_type = AMDGPU_PL_NPA;
places[c].flags = 0;
c++;
}
if (!c) {
places[c].fpfn = 0;
places[c].lpfn = 0;
@ -1663,6 +1671,9 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
case AMDGPU_PL_MMIO_REMAP:
placement = "MMIO REMAP";
break;
case AMDGPU_PL_NPA:
placement = "NPA";
break;
case TTM_PL_SYSTEM:
default:
placement = "CPU";

2
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
View File

@ -169,6 +169,8 @@ static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
return AMDGPU_GEM_DOMAIN_OA;
case AMDGPU_PL_DOORBELL:
return AMDGPU_GEM_DOMAIN_DOORBELL;
case AMDGPU_PL_NPA:
return AMDGPU_GEM_DOMAIN_NPA;
default:
break;
}

17
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View File

@ -129,6 +129,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
case AMDGPU_PL_OA:
case AMDGPU_PL_DOORBELL:
case AMDGPU_PL_MMIO_REMAP:
case AMDGPU_PL_NPA:
placement->num_placement = 0;
return;
@ -580,11 +581,13 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
old_mem->mem_type == AMDGPU_PL_OA ||
old_mem->mem_type == AMDGPU_PL_DOORBELL ||
old_mem->mem_type == AMDGPU_PL_MMIO_REMAP ||
old_mem->mem_type == AMDGPU_PL_NPA ||
new_mem->mem_type == AMDGPU_PL_GDS ||
new_mem->mem_type == AMDGPU_PL_GWS ||
new_mem->mem_type == AMDGPU_PL_OA ||
new_mem->mem_type == AMDGPU_PL_DOORBELL ||
new_mem->mem_type == AMDGPU_PL_MMIO_REMAP) {
new_mem->mem_type == AMDGPU_PL_MMIO_REMAP ||
new_mem->mem_type == AMDGPU_PL_NPA) {
/* Nothing to save here */
amdgpu_bo_move_notify(bo, evict, new_mem);
ttm_bo_move_null(bo, new_mem);
@ -2277,6 +2280,16 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
dev_err(adev->dev, "Failed initializing oa heap.\n");
return r;
}
if (adev->ualink.npa_size) {
r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_NPA,
adev->ualink.npa_size);
if (r) {
dev_err(adev->dev, "Failed initializing NPA heap.\n");
return r;
}
}
if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_GTT,
&adev->mman.sdma_access_bo, NULL,
@ -2330,6 +2343,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DOORBELL);
ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_MMIO_REMAP);
ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_NPA);
ttm_device_fini(&adev->mman.bdev);
adev->mman.initialized = false;
dev_info(adev->dev, " ttm finalized\n");
@ -2712,6 +2726,7 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
case AMDGPU_PL_GWS:
case AMDGPU_PL_GDS:
case AMDGPU_PL_OA:
case AMDGPU_PL_NPA:
man = ttm_manager_type(&adev->mman.bdev, mem_type);
break;
default:

4
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
View File

@ -37,7 +37,9 @@
#define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3)
#define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4)
#define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5)
#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6)
#define AMDGPU_PL_NPA (TTM_PL_PRIV + 6)
#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 7)
#define AMDGPU_GTT_MAX_TRANSFER_SIZE (1ULL << 22)

1
drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h
View File

@ -133,6 +133,7 @@ struct amdgpu_ualink_connection {
};
struct amdgpu_ualink_mgr {
u64 npa_size;
u32 psp_if_ver;
struct amdgpu_ualink_info *info;
struct amdgpu_ualink_ppod_setup *setup;

5
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
View File

@ -3195,6 +3195,11 @@ static int gfx_v12_1_early_init(struct amdgpu_ip_block *ip_block)
amdgpu_init_rlc_reg_funcs(adev);
/* Set NPA address size here as its needed in amdgpu_ttm_init().
* NPA address space is 52 bits or 2^40 pages long.
*/
adev->ualink.npa_size = 1ULL << 40;
return gfx_v12_1_init_microcode(adev);
}

2
include/drm/ttm/ttm_resource.h
View File

@ -35,7 +35,7 @@
#include <drm/ttm/ttm_kmap_iter.h>
#define TTM_MAX_BO_PRIORITY 4U
#define TTM_NUM_MEM_TYPES 9
#define TTM_NUM_MEM_TYPES 10
struct dentry;
struct dmem_cgroup_device;

6
include/uapi/drm/amdgpu_drm.h
View File

@ -115,6 +115,12 @@ extern "C" {
#define AMDGPU_GEM_DOMAIN_GWS 0x10
#define AMDGPU_GEM_DOMAIN_OA 0x20
#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
#define AMDGPU_GEM_DOMAIN_MMIO_REMAP 0x80
#define AMDGPU_GEM_DOMAIN_NPA 0x100
/* User-mode is not allowed to allocate NPA space. As a result,
* we don't add AMDGPU_GEM_DOMAIN_NPA in the DOMAIN_MASK below.
*/
#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
AMDGPU_GEM_DOMAIN_GTT | \
AMDGPU_GEM_DOMAIN_VRAM | \