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drm/i915/wm: Use skl_prefill
Replace the current ad-hoc prefill calculations with skl_prefill.
v2: cdclk_state no longer needed
Rename to skl_prefill
Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251014191808.12326-10-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä
parent
ba470a99f2
commit
08c54f3c83
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@ -30,6 +30,7 @@
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#include "intel_plane.h"
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#include "intel_vblank.h"
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#include "intel_wm.h"
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#include "skl_prefill.h"
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#include "skl_scaler.h"
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#include "skl_universal_plane_regs.h"
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#include "skl_watermark.h"
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@ -2147,105 +2148,6 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
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return 0;
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}
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static int
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cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_atomic_state *state =
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to_intel_atomic_state(crtc_state->uapi.state);
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const struct intel_cdclk_state *cdclk_state;
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cdclk_state = intel_atomic_get_cdclk_state(state);
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if (IS_ERR(cdclk_state)) {
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drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
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return 1;
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}
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return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
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2 * intel_cdclk_logical(cdclk_state)));
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}
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static int
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dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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const struct intel_crtc_scaler_state *scaler_state =
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&crtc_state->scaler_state;
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int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
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crtc_state->hw.adjusted_mode.clock);
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int num_scaler_users = hweight32(scaler_state->scaler_users);
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int chroma_downscaling_factor =
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crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
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u32 dsc_prefill_latency = 0;
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if (!crtc_state->dsc.compression_enable ||
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!num_scaler_users ||
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num_scaler_users > crtc->num_scalers)
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return dsc_prefill_latency;
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dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
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for (int i = 0; i < num_scaler_users; i++) {
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u64 hscale_k, vscale_k;
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hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
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vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
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dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k,
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1000000);
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}
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dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
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return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency);
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}
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static int
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scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
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{
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const struct intel_crtc_scaler_state *scaler_state =
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&crtc_state->scaler_state;
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int num_scaler_users = hweight32(scaler_state->scaler_users);
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int scaler_prefill_latency = 0;
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int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
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crtc_state->hw.adjusted_mode.clock);
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if (!num_scaler_users)
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return scaler_prefill_latency;
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scaler_prefill_latency = 4 * linetime;
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if (num_scaler_users > 1) {
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u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
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u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
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int chroma_downscaling_factor =
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crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
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int latency;
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latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
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chroma_downscaling_factor), 1000000);
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scaler_prefill_latency += latency;
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}
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scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
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return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency);
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}
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static bool
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skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
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int wm0_lines, int latency)
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{
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const struct drm_display_mode *adjusted_mode =
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&crtc_state->hw.adjusted_mode;
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return crtc_state->framestart_delay +
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intel_usecs_to_scanlines(adjusted_mode, latency) +
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scaler_prefill_latency(crtc_state) +
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dsc_prefill_latency(crtc_state) +
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wm0_lines >
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intel_crtc_vblank_length(crtc_state);
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}
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unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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@ -2324,9 +2226,10 @@ unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state)
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* the scenario to apply Wa_16025596647.
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*/
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static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
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int wm0_lines)
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const struct skl_prefill_ctx *ctx)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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int level;
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for (level = display->wm.num_levels - 1; level >= 0; level--) {
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@ -2341,10 +2244,13 @@ static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
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if (level == 0)
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latency = 0;
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if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency))
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if (!skl_prefill_vblank_too_short(ctx, crtc_state, latency))
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return level;
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}
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drm_dbg_kms(display->drm, "[CRTC:%d:%s] Not enough time in vblank for prefill\n",
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crtc->base.base.id, crtc->base.name);
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return -EINVAL;
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}
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@ -2352,14 +2258,15 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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int wm0_lines, level;
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struct skl_prefill_ctx ctx;
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int level;
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if (!crtc_state->hw.active)
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return 0;
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wm0_lines = skl_max_wm0_lines(crtc_state);
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skl_prefill_init(&ctx, crtc_state);
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level = skl_max_wm_level_for_vblank(crtc_state, wm0_lines);
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level = skl_max_wm_level_for_vblank(crtc_state, &ctx);
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if (level < 0)
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return level;
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@ -2369,6 +2276,13 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
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*/
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crtc_state->wm_level_disabled = level < display->wm.num_levels - 1;
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/*
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* TODO: assert that we are in fact using the maximum guardband
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* if we end up disabling any WM levels here. Otherwise we clearly
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* failed in using a realistic worst case prefill estimate when
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* determining the guardband size.
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*/
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for (level++; level < display->wm.num_levels; level++) {
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enum plane_id plane_id;
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@ -2387,8 +2301,8 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
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if (DISPLAY_VER(display) >= 12 &&
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display->sagv.block_time_us &&
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skl_is_vblank_too_short(crtc_state, wm0_lines,
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display->sagv.block_time_us)) {
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skl_prefill_vblank_too_short(&ctx, crtc_state,
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display->sagv.block_time_us)) {
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enum plane_id plane_id;
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for_each_plane_id_on_crtc(crtc, plane_id) {
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