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Merge branch 'octeontx2-af-npc-parser-and-rss-improvements'

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Kiran Kumar says:

====================
octeontx2-af: NPC parser and RSS improvements

This series extends the Marvell OcteonTX2 admin-function driver with two
improvements to the NPC (Network Parser CAM) block. The NPC parses packets
received by or transmitted from the NIX, and its matching CAM (MCAM)
selects which VFs, queues, or output ports handle each packet.

Patch 1 reserves a new range of PKINDs (46-53) to support configurable
L2 skip-size parsing. Packets arriving with variable length L2 headers
or a CPT (Cryptographic Accelerator Unit) pre-header can be steered
to one of four skip-size PKINDs so the NPC advances past the right number
of bytes before starting protocol classification. The mbox interface is
extended with a skip_size field so PF/VF drivers can program the desired
L2 offset at run time without rebuilding firmware.

Patch 2 adds a NIX_FLOW_KEY_TYPE_ROCEV2 flow-key type so the RSS engine
can distribute RoCEv2 traffic across receive queues using the destination
Queue Pair (QP) field. Without this, all RoCEv2 flows hash the same
way and land on a single queue.

Both changes target the admin-function driver to improve overall hardware
parsing infrastructure.
====================

Link: https://patch.msgid.link/20260630062145.2533816-1-nshettyj@marvell.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni 2026-07-02 15:11:38 +02:00
commit 08bc5b2636
5 changed files with 54 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
View File

@ -803,6 +803,7 @@ struct npc_set_pkind {
*/
u8 var_len_off_mask; /* Mask for length with in offset */
u8 shift_dir; /* shift direction to get length of the header at var_len_off */
u8 skip_size; /* l2 size to skip */
};
/* NPA mbox message formats */
@ -1267,6 +1268,7 @@ struct nix_rss_flowkey_cfg {
#define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
#define NIX_FLOW_KEY_TYPE_AH BIT(22)
#define NIX_FLOW_KEY_TYPE_ESP BIT(23)
#define NIX_FLOW_KEY_TYPE_ROCEV2 BIT(24)
#define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28)
#define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29)
#define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30)

4
drivers/net/ethernet/marvell/octeontx2/af/npc.h
View File

@ -161,10 +161,12 @@ enum npc_kpu_lh_ltype {
* Software assigns pkind for each incoming port such as CGX
* Ethernet interfaces, LBK interfaces, etc.
*/
#define NPC_UNRESERVED_PKIND_COUNT NPC_RX_CPT_HDR_PTP_PKIND
#define NPC_UNRESERVED_PKIND_COUNT NPC_RX_SKIP_SIZE_PKIND
enum npc_pkind_type {
NPC_RX_LBK_PKIND = 0ULL,
NPC_RX_SKIP_SIZE_PKIND = 46ULL,
NPC_RX_CPT_SKIP_SIZE_PKIND = 50ULL,
NPC_RX_CPT_HDR_PTP_PKIND = 54ULL,
NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,
NPC_RX_VLAN_EXDSA_PKIND = 56ULL,

2
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
View File

@ -1181,7 +1181,7 @@ void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool ena);
int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
u64 pkind, u8 var_len_off, u8 var_len_off_mask,
u8 shift_dir);
u8 shift_dir, u8 skip_size);
int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
/* CN10K MCS */

9
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
View File

@ -4305,6 +4305,13 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg)
keyoff_marker = false;
}
break;
case NIX_FLOW_KEY_TYPE_ROCEV2:
field->hdr_offset = 5;
field->bytesm1 = 2; /* Destination QP */
field->ltype_mask = 0xF;
field->lid = NPC_LID_LE;
field->ltype_match = NPC_LT_LE_ROCEV2;
break;
}
field->ena = 1;
@ -5392,7 +5399,7 @@ void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int nixlf)
/* reset HW config done for Switch headers */
rvu_npc_set_parse_mode(rvu, pcifunc, OTX2_PRIV_FLAGS_DEFAULT,
(PKIND_TX | PKIND_RX), 0, 0, 0, 0);
(PKIND_TX | PKIND_RX), 0, 0, 0, 0, 0);
/* Disabling CGX and NPC config done for PTP */
if (pfvf->hw_rx_tstamp_en) {

43
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
View File

@ -4194,10 +4194,40 @@ npc_set_var_len_offset_pkind(struct rvu *rvu, u16 pcifunc, u64 pkind,
return 0;
}
static int npc_set_skip_size_pkind(struct rvu *rvu, u16 pcifunc, u64 pkind,
u8 skip_size)
{
struct npc_kpu_action0 *act0;
int blkaddr;
u64 val;
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc);
if (blkaddr < 0) {
dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
return -EINVAL;
}
val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind));
act0 = (struct npc_kpu_action0 *)&val;
act0->ptr_advance = skip_size;
rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val);
/* Update CPT_HR new PKIND */
val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind + 4));
act0 = (struct npc_kpu_action0 *)&val;
act0->ptr_advance = (skip_size + 40);
act0->next_state = NPC_S_KPU1_CPT_HDR;
act0->var_len_offset = (skip_size + 6);
act0->var_len_mask = 0xe0;
act0->var_len_shift = 0x5;
act0->var_len_right = 0x1;
rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind + 4), val);
return 0;
}
int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
u64 pkind, u8 var_len_off, u8 var_len_off_mask,
u8 shift_dir)
u8 shift_dir, u8 skip_size)
{
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
int blkaddr, nixlf, rc, intf_mode;
@ -4218,6 +4248,12 @@ int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
shift_dir);
if (rc)
return rc;
} else if (pkind >= NPC_RX_SKIP_SIZE_PKIND &&
pkind <= NPC_RX_SKIP_SIZE_PKIND + 3) {
rc = npc_set_skip_size_pkind(rvu, pcifunc, pkind,
skip_size);
if (rc)
return rc;
}
rxpkind = pkind;
txpkind = pkind;
@ -4254,7 +4290,8 @@ int rvu_mbox_handler_npc_set_pkind(struct rvu *rvu, struct npc_set_pkind *req,
{
return rvu_npc_set_parse_mode(rvu, req->hdr.pcifunc, req->mode,
req->dir, req->pkind, req->var_len_off,
req->var_len_off_mask, req->shift_dir);
req->var_len_off_mask, req->shift_dir,
req->skip_size);
}
int rvu_mbox_handler_npc_read_base_steer_rule(struct rvu *rvu,