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Merge branch 'octeontx2-pf-do-not-detect-macsec-block-based-on-silicon'

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Subbaraya Sundeep says:

====================
octeontx2-pf: Do not detect MACSEC block based on silicon

Out of various silicon variants of CN10K series some have hardware
MACSEC block for offloading MACSEC operations and some do not.
AF driver already has the information of whether MACSEC is present
or not on running silicon. Hence fetch that information from
AF via mailbox message.
====================

Link: https://patch.msgid.link/1747894516-4565-1-git-send-email-sbhatta@marvell.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni 2025-05-27 11:54:55 +02:00
commit 08ae62e172
5 changed files with 45 additions and 3 deletions
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2
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
View File

@ -524,6 +524,8 @@ struct get_hw_cap_rsp {
u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
u8 nix_shaping; /* Is shaping and coloring supported */
u8 npc_hash_extract; /* Is hash extract supported */
#define HW_CAP_MACSEC BIT_ULL(1)
u64 hw_caps;
};
/* CGX mbox message formats */

3
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
View File

@ -2033,6 +2033,9 @@ int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req,
rsp->nix_shaping = hw->cap.nix_shaping;
rsp->npc_hash_extract = hw->cap.npc_hash_extract;
if (rvu->mcs_blk_cnt)
rsp->hw_caps = HW_CAP_MACSEC;
return 0;
}

37
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
View File

@ -2055,6 +2055,43 @@ int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t
}
EXPORT_SYMBOL(otx2_handle_ntuple_tc_features);
int otx2_set_hw_capabilities(struct otx2_nic *pfvf)
{
struct mbox *mbox = &pfvf->mbox;
struct otx2_hw *hw = &pfvf->hw;
struct get_hw_cap_rsp *rsp;
struct msg_req *req;
int ret = -ENOMEM;
mutex_lock(&mbox->lock);
req = otx2_mbox_alloc_msg_get_hw_cap(mbox);
if (!req)
goto fail;
ret = otx2_sync_mbox_msg(mbox);
if (ret)
goto fail;
rsp = (struct get_hw_cap_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox,
0, &req->hdr);
if (IS_ERR(rsp)) {
ret = -EINVAL;
goto fail;
}
if (rsp->hw_caps & HW_CAP_MACSEC)
__set_bit(CN10K_HW_MACSEC, &hw->cap_flag);
mutex_unlock(&mbox->lock);
return 0;
fail:
dev_err(pfvf->dev, "Cannot get MACSEC capability from AF\n");
mutex_unlock(&mbox->lock);
return ret;
}
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
int __weak \
otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \

4
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
View File

@ -632,9 +632,6 @@ static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
__set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag);
__set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag);
}
if (is_dev_cn10kb(pfvf->pdev))
__set_bit(CN10K_HW_MACSEC, &hw->cap_flag);
}
/* Register read/write APIs */
@ -1046,6 +1043,7 @@ void otx2_disable_napi(struct otx2_nic *pf);
irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq);
int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura);
int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx);
int otx2_set_hw_capabilities(struct otx2_nic *pfvf);
/* RSS configuration APIs*/
int otx2_rss_init(struct otx2_nic *pfvf);

2
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
View File

@ -3144,6 +3144,8 @@ static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (err)
goto err_ptp_destroy;
otx2_set_hw_capabilities(pf);
err = cn10k_mcs_init(pf);
if (err)
goto err_del_mcam_entries;