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soc: fsl: qe: Iterate over all pending interrupts in cascade handler
Instead of only servicing a single interrupt, the chained handler can handle all IRQs that have their bit set in the event register. This avoid multiple parent IRQ handler being serviced if more than one interrupt are pending on the QE PIC. Remove unused code. Signed-off-by: Paul Louvel <paul.louvel@bootlin.com> Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> Link: https://lore.kernel.org/r/20260708-qe-pic-gpios-v2-6-1972044cfbd1@bootlin.com Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
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@ -5,6 +5,7 @@
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* Copyright (c) 2025 Christophe Leroy CS GROUP France (christophe.leroy@csgroup.eu)
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*/
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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@ -70,25 +71,17 @@ static struct irq_chip qepic = {
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.irq_set_type = qepic_set_type,
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};
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static int qepic_get_irq(struct irq_desc *desc)
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{
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struct qepic_data *data = irq_desc_get_handler_data(desc);
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u32 event = ioread32be(data->reg + CEPIER);
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if (!event)
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return -1;
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return 32 - ffs(event);
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}
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static void qepic_cascade(struct irq_desc *desc)
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{
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struct qepic_data *data = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long event, bit;
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chained_irq_enter(chip, desc);
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generic_handle_domain_irq(data->host, qepic_get_irq(desc));
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event = ioread32be(data->reg + CEPIER);
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for_each_set_bit(bit, &event, 32)
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generic_handle_domain_irq(data->host, 31 - bit);
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chained_irq_exit(chip, desc);
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}
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