soc: fsl: qe: Iterate over all pending interrupts in cascade handler

Instead of only servicing a single interrupt, the chained handler can
handle all IRQs that have their bit set in the event register.
This avoid multiple parent IRQ handler being serviced if more than one
interrupt are pending on the QE PIC.

Remove unused code.

Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Link: https://lore.kernel.org/r/20260708-qe-pic-gpios-v2-6-1972044cfbd1@bootlin.com
Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
This commit is contained in:
Paul Louvel 2026-07-08 12:15:19 +02:00 committed by Christophe Leroy (CS GROUP)
parent 9727108464
commit 0887d5f68c

View File

@ -5,6 +5,7 @@
* Copyright (c) 2025 Christophe Leroy CS GROUP France (christophe.leroy@csgroup.eu)
*/
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
@ -70,25 +71,17 @@ static struct irq_chip qepic = {
.irq_set_type = qepic_set_type,
};
static int qepic_get_irq(struct irq_desc *desc)
{
struct qepic_data *data = irq_desc_get_handler_data(desc);
u32 event = ioread32be(data->reg + CEPIER);
if (!event)
return -1;
return 32 - ffs(event);
}
static void qepic_cascade(struct irq_desc *desc)
{
struct qepic_data *data = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long event, bit;
chained_irq_enter(chip, desc);
generic_handle_domain_irq(data->host, qepic_get_irq(desc));
event = ioread32be(data->reg + CEPIER);
for_each_set_bit(bit, &event, 32)
generic_handle_domain_irq(data->host, 31 - bit);
chained_irq_exit(chip, desc);
}