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arm64: dts: qcom: sm6125: Add display hardware nodes
Add the DT nodes that describe the MDSS hardware on SM6125, containing one MDP (display controller) together with a single DSI and DSI PHY. No DisplayPort support is added for now. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-16-a3f287dd6c07@somainline.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Marijn Suijten
Bjorn Andersson
parent
4988881ec0
commit
0865d23a02
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@ -1208,13 +1208,202 @@ sram@4690000 {
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reg = <0x04690000 0x10000>;
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reg = <0x04690000 0x10000>;
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};
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};
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mdss: display-subsystem@5e00000 {
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compatible = "qcom,sm6125-mdss";
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reg = <0x05e00000 0x1000>;
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reg-names = "mdss";
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface",
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"ahb",
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"core";
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power-domains = <&dispcc MDSS_GDSC>;
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iommus = <&apps_smmu 0x400 0x0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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mdss_mdp: display-controller@5e01000 {
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compatible = "qcom,sm6125-dpu";
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reg = <0x05e01000 0x83208>,
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<0x05eb0000 0x2008>;
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reg-names = "mdp", "vbif";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
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<&gcc GCC_DISP_THROTTLE_CORE_CLK>;
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clock-names = "bus",
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"iface",
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"rot",
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"lut",
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"core",
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"vsync",
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"throttle";
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assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmpd SM6125_VDDCX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-192000000 {
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opp-hz = /bits/ 64 <192000000>;
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required-opps = <&rpmpd_opp_low_svs>;
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};
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opp-256000000 {
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opp-hz = /bits/ 64 <256000000>;
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required-opps = <&rpmpd_opp_svs>;
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};
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opp-307200000 {
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opp-hz = /bits/ 64 <307200000>;
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required-opps = <&rpmpd_opp_svs_plus>;
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};
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opp-384000000 {
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opp-hz = /bits/ 64 <384000000>;
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required-opps = <&rpmpd_opp_nom>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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required-opps = <&rpmpd_opp_turbo>;
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};
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};
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};
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mdss_dsi0: dsi@5e94000 {
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compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x05e94000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmpd SM6125_VDDCX>;
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phys = <&mdss_dsi0_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi0_out: endpoint {
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};
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};
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};
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dsi_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-164000000 {
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opp-hz = /bits/ 64 <164000000>;
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required-opps = <&rpmpd_opp_low_svs>;
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};
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opp-187500000 {
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opp-hz = /bits/ 64 <187500000>;
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required-opps = <&rpmpd_opp_svs>;
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};
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};
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};
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mdss_dsi0_phy: phy@5e94400 {
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compatible = "qcom,sm6125-dsi-phy-14nm";
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reg = <0x05e94400 0x100>,
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<0x05e94500 0x300>,
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<0x05e94800 0x188>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmcc RPM_SMD_XO_CLK_SRC>;
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clock-names = "iface",
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"ref";
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required-opps = <&rpmpd_opp_nom>;
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power-domains = <&rpmpd SM6125_VDDMX>;
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status = "disabled";
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};
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};
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dispcc: clock-controller@5f00000 {
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dispcc: clock-controller@5f00000 {
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compatible = "qcom,sm6125-dispcc";
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compatible = "qcom,sm6125-dispcc";
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reg = <0x05f00000 0x20000>;
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reg = <0x05f00000 0x20000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<0>,
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<&mdss_dsi0_phy 0>,
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<0>,
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<&mdss_dsi0_phy 1>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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