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arm64: dts: qcom: sm6125: Add display hardware nodes

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Add the DT nodes that describe the MDSS hardware on SM6125, containing
one MDP (display controller) together with a single DSI and DSI PHY.  No
DisplayPort support is added for now.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-16-a3f287dd6c07@somainline.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Marijn Suijten 2023-07-23 18:08:54 +02:00 committed by Bjorn Andersson
parent 4988881ec0
commit 0865d23a02
1 changed files with 191 additions and 2 deletions
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193
arch/arm64/boot/dts/qcom/sm6125.dtsi
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@ -1208,13 +1208,202 @@ sram@4690000 {
reg = <0x04690000 0x10000>;
};
mdss: display-subsystem@5e00000 {
compatible = "qcom,sm6125-mdss";
reg = <0x05e00000 0x1000>;
reg-names = "mdss";
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface",
"ahb",
"core";
power-domains = <&dispcc MDSS_GDSC>;
iommus = <&apps_smmu 0x400 0x0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
mdss_mdp: display-controller@5e01000 {
compatible = "qcom,sm6125-dpu";
reg = <0x05e01000 0x83208>,
<0x05eb0000 0x2008>;
reg-names = "mdp", "vbif";
interrupt-parent = <&mdss>;
interrupts = <0>;
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&gcc GCC_DISP_THROTTLE_CORE_CLK>;
clock-names = "bus",
"iface",
"rot",
"lut",
"core",
"vsync",
"throttle";
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmpd SM6125_VDDCX>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-256000000 {
opp-hz = /bits/ 64 <256000000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
required-opps = <&rpmpd_opp_svs_plus>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmpd_opp_nom>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
required-opps = <&rpmpd_opp_turbo>;
};
};
};
mdss_dsi0: dsi@5e94000 {
compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x05e94000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd SM6125_VDDCX>;
phys = <&mdss_dsi0_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-164000000 {
opp-hz = /bits/ 64 <164000000>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmpd_opp_svs>;
};
};
};
mdss_dsi0_phy: phy@5e94400 {
compatible = "qcom,sm6125-dsi-phy-14nm";
reg = <0x05e94400 0x100>,
<0x05e94500 0x300>,
<0x05e94800 0x188>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface",
"ref";
required-opps = <&rpmpd_opp_nom>;
power-domains = <&rpmpd SM6125_VDDMX>;
status = "disabled";
};
};
dispcc: clock-controller@5f00000 {
compatible = "qcom,sm6125-dispcc";
reg = <0x05f00000 0x20000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<0>,
<0>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<0>,
<0>,
<0>,