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drm/amd/display: Fix Display Flicker on embedded panels

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[Why]
ASSR is dependent on Signed PSP Verstage to enable Content
Protection for eDP panels. Unsigned PSP verstage is used
during development phase causing ASSR to FAIL.
As a result, link training is performed with
DP_PANEL_MODE_DEFAULT instead of DP_PANEL_MODE_EDP for
eDP panels that causes display flicker on some panels.

[How]
- Do not change panel mode, if ASSR is disabled
- Just report and continue to perform eDP link training
with right settings further.

Signed-off-by: Praful Swarnakar <Praful.Swarnakar@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Praful Swarnakar 2021-09-22 23:01:29 +05:30 committed by Alex Deucher
parent 66805763a9
commit 083fa05bba
1 changed files with 7 additions and 8 deletions
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15
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -1826,14 +1826,13 @@ bool perform_link_training_with_retries(
if (panel_mode == DP_PANEL_MODE_EDP) {
struct cp_psp *cp_psp = &stream->ctx->cp_psp;
if (cp_psp && cp_psp->funcs.enable_assr) {
if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
/* since eDP implies ASSR on, change panel
* mode to disable ASSR
*/
panel_mode = DP_PANEL_MODE_DEFAULT;
}
}
if (cp_psp && cp_psp->funcs.enable_assr)
/* ASSR is bound to fail with unsigned PSP
* verstage used during devlopment phase.
* Report and continue with eDP panel mode to
* perform eDP link training with right settings
*/
cp_psp->funcs.enable_assr(cp_psp->handle, link);
}
#endif