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drm/amd/ras: update flip bit setting for uniras

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The flip bit setting is different if umc number is 8, only NPS1 and
NPS2 are supported in this mode.

Note: the typical value of umc number is 16, and it can only be 8 or 16
on umc v12.

v2: if other umc number is encountered, default setting will be
used.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tao Zhou 2026-07-06 17:21:39 +08:00 committed by Alex Deucher
parent 314d49abe3
commit 0827279ac1
5 changed files with 79 additions and 28 deletions
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1
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
View File

@ -284,6 +284,7 @@ static int amdgpu_ras_mgr_init_umc_config(struct amdgpu_device *adev,
struct ras_umc_config *umc_cfg = &config->umc_cfg;
umc_cfg->umc_vram_type = adev->gmc.vram_type;
umc_cfg->num_umc = adev->gmc.num_umc;
return 0;
}

1
drivers/gpu/drm/amd/ras/rascore/ras.h
View File

@ -278,6 +278,7 @@ struct ras_psp_config {
struct ras_umc_config {
uint32_t umc_vram_type;
uint32_t num_umc;
};
struct ras_eeprom_config {

1
drivers/gpu/drm/amd/ras/rascore/ras_umc.c
View File

@ -691,6 +691,7 @@ int ras_umc_hw_init(struct ras_core_context *ras_core)
ras_umc->umc_err_data.umc_nps_mode = nps;
ras_umc->umc_vram_type = ras_core->config->umc_cfg.umc_vram_type;
ras_umc->num_umc = ras_core->config->umc_cfg.num_umc;
if (!ras_umc->umc_vram_type) {
RAS_DEV_ERR(ras_core->dev, "Invalid UMC VRAM Type: %u!\n",
ras_umc->umc_vram_type);

1
drivers/gpu/drm/amd/ras/rascore/ras_umc.h
View File

@ -137,6 +137,7 @@ struct ras_umc_err_data {
struct ras_umc {
u32 umc_ip_version;
u32 umc_vram_type;
u32 num_umc;
const struct ras_umc_ip_func *ip_func;
struct radix_tree_root root;
struct mutex tree_lock;

103
drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
View File

@ -64,6 +64,7 @@ static void __get_nps_pa_flip_bits(struct ras_core_context *ras_core,
struct umc_flip_bits *flip_bits)
{
uint32_t vram_type = ras_core->ras_umc.umc_vram_type;
u32 num_umc = ras_core->ras_umc.num_umc;
/* default setting */
flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT;
@ -74,41 +75,87 @@ static void __get_nps_pa_flip_bits(struct ras_core_context *ras_core,
flip_bits->bit_num = 4;
flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT;
if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) {
if (num_umc == 16) {
if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) {
flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;
} else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) {
flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
}
switch (vram_type) {
case UMC_VRAM_TYPE_HBM:
/* other nps modes are taken as nps1 */
if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4)
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
break;
case UMC_VRAM_TYPE_HBM3E:
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
flip_bits->flip_row_bit = 12;
if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4)
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;
break;
default:
RAS_DEV_WARN(ras_core->dev,
"Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");
break;
}
} else if (num_umc == 8) {
/* num_umc == 8 base setting */
flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;
} else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) {
flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
}
switch (vram_type) {
case UMC_VRAM_TYPE_HBM:
/* other nps modes are taken as nps1 */
if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4)
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
break;
case UMC_VRAM_TYPE_HBM3E:
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
flip_bits->flip_row_bit = 12;
flip_bits->bit_num = 4;
flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;
if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4)
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;
/* only NPS1 and NPS2 are supported in this mode */
if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) {
flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
}
break;
default:
switch (vram_type) {
case UMC_VRAM_TYPE_HBM:
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
/* other nps modes are taken as nps1 */
if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
break;
case UMC_VRAM_TYPE_HBM3E:
if (nps == UMC_MEMORY_PARTITION_MODE_NPS2)
flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;
break;
default:
RAS_DEV_WARN(ras_core->dev,
"Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");
break;
}
} else {
/* num_umc is always 8 or 16 on umc v12, this path should not be
* entered.
*/
RAS_DEV_WARN(ras_core->dev,
"Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");
break;
"Unsupported UMC number(%u), use default RAS flip bits setting.\n",
num_umc);
}
}