From 07bd391eb9572e74f073c49acef327611234f9bb Mon Sep 17 00:00:00 2001 From: Alok Tiwari Date: Sun, 11 Oct 2026 05:54:59 -0700 Subject: [PATCH] octeontx2-af: Fix CQ enable state tracking after AQ writes Use the CQ context's ena field when updating the CQ enable bitmap. The current code reads rq.ena, which overlaps bit 0 of the CQ base address and can leave the bitmap out of sync with the hardware context. This can cause enabled CQs to be skipped during teardown. Use sq.ena for the SQ bitmap update as well, so each queue type reads its own context. Fixes: 557dd485eaeb ("octeontx2-af: Support for disabling NIX RQ/SQ/CQ contexts") Signed-off-by: Alok Tiwari Reviewed-by: Ratheesh Kannoth Reviewed-by: Sunil Goutham Link: https://patch.msgid.link/20261011125508.534618-1-alok.a.tiwari@oracle.com Signed-off-by: Paolo Abeni --- drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c index 153eb57bad06..95f782d47927 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -1239,7 +1239,7 @@ static int rvu_nix_blk_aq_enq_inst(struct rvu *rvu, struct nix_hw *nix_hw, __clear_bit(req->qidx, pfvf->rq_bmap); } if (req->ctype == NIX_AQ_CTYPE_SQ) { - ena = (req->rq.ena & req->sq_mask.ena) | + ena = (req->sq.ena & req->sq_mask.ena) | (test_bit(req->qidx, pfvf->sq_bmap) & ~req->sq_mask.ena); if (ena) @@ -1248,7 +1248,7 @@ static int rvu_nix_blk_aq_enq_inst(struct rvu *rvu, struct nix_hw *nix_hw, __clear_bit(req->qidx, pfvf->sq_bmap); } if (req->ctype == NIX_AQ_CTYPE_CQ) { - ena = (req->rq.ena & req->cq_mask.ena) | + ena = (req->cq.ena & req->cq_mask.ena) | (test_bit(req->qidx, pfvf->cq_bmap) & ~req->cq_mask.ena); if (ena)