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clk: qcom: tcsrcc-glymur: Add regulator supplies and migrate to clk_ref helper

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Replace local clk_branch-based clkref definitions with descriptor-based
registration via qcom_clk_ref_probe().

This keeps the glymur driver focused on clock metadata and reuses common
runtime logic for regulator handling, enable/disable sequencing, and OF
provider wiring.

Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260721-tcsr_qre_0721-v10-4-d2fa68c63b78@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Qiang Yu 2026-07-21 22:58:59 -07:00 committed by Bjorn Andersson
parent 22c70e5732
commit 0753091abc
1 changed files with 118 additions and 247 deletions
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365
drivers/clk/qcom/tcsrcc-glymur.c
View File

@ -4,263 +4,57 @@
*/
#include <linux/clk-provider.h>
#include <linux/clk/qcom.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,glymur-tcsr.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO_PAD,
static const char * const glymur_tcsr_tx0_rx5_regulators[] = {
"vdda-refgen3-0p9",
"vdda-refgen3-1p2",
"vdda-qrefrx5-0p9",
"vdda-qreftx0-0p9",
"vdda-qreftx0-1p2",
};
static struct clk_branch tcsr_edp_clkref_en = {
.halt_reg = 0x60,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x60,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_edp_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const glymur_tcsr_tx1_rpt0_rx0_regulators[] = {
"vdda-refgen4-0p9",
"vdda-refgen4-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt0-0p9",
"vdda-qrefrx0-0p9",
};
static struct clk_branch tcsr_pcie_1_clkref_en = {
.halt_reg = 0x48,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x48,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const glymur_tcsr_tx1_rpt01_rx1_regulators[] = {
"vdda-refgen4-0p9",
"vdda-refgen4-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt0-0p9",
"vdda-qrefrpt1-0p9",
"vdda-qrefrx1-0p9",
};
static struct clk_branch tcsr_pcie_2_clkref_en = {
.halt_reg = 0x4c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x4c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const glymur_tcsr_tx1_rpt012_rx2_regulators[] = {
"vdda-refgen4-0p9",
"vdda-refgen4-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt0-0p9",
"vdda-qrefrpt1-0p9",
"vdda-qrefrpt2-0p9",
"vdda-qrefrx2-0p9",
};
static struct clk_branch tcsr_pcie_3_clkref_en = {
.halt_reg = 0x54,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x54,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_3_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_4_clkref_en = {
.halt_reg = 0x58,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x58,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_4_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_1_clkref_en = {
.halt_reg = 0x6c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x6c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_2_clkref_en = {
.halt_reg = 0x70,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x70,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_3_clkref_en = {
.halt_reg = 0x74,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x74,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_3_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_4_clkref_en = {
.halt_reg = 0x88,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x88,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_4_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_0_clkref_en = {
.halt_reg = 0x64,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x64,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_0_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_1_clkref_en = {
.halt_reg = 0x68,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb4_1_clkref_en = {
.halt_reg = 0x44,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x44,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb4_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb4_2_clkref_en = {
.halt_reg = 0x5c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb4_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *tcsr_cc_glymur_clocks[] = {
[TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr,
[TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
[TCSR_PCIE_2_CLKREF_EN] = &tcsr_pcie_2_clkref_en.clkr,
[TCSR_PCIE_3_CLKREF_EN] = &tcsr_pcie_3_clkref_en.clkr,
[TCSR_PCIE_4_CLKREF_EN] = &tcsr_pcie_4_clkref_en.clkr,
[TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr,
[TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr,
[TCSR_USB2_3_CLKREF_EN] = &tcsr_usb2_3_clkref_en.clkr,
[TCSR_USB2_4_CLKREF_EN] = &tcsr_usb2_4_clkref_en.clkr,
[TCSR_USB3_0_CLKREF_EN] = &tcsr_usb3_0_clkref_en.clkr,
[TCSR_USB3_1_CLKREF_EN] = &tcsr_usb3_1_clkref_en.clkr,
[TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr,
[TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr,
static const char * const glymur_tcsr_tx1_rpt34_rx4_regulators[] = {
"vdda-refgen4-0p9",
"vdda-refgen4-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt3-0p9",
"vdda-qrefrpt4-0p9",
"vdda-qrefrx4-0p9",
};
static const struct regmap_config tcsr_cc_glymur_regmap_config = {
@ -271,10 +65,85 @@ static const struct regmap_config tcsr_cc_glymur_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_desc tcsr_cc_glymur_desc = {
.config = &tcsr_cc_glymur_regmap_config,
.clks = tcsr_cc_glymur_clocks,
.num_clks = ARRAY_SIZE(tcsr_cc_glymur_clocks),
static const struct qcom_clk_ref_desc * const tcsr_cc_glymur_clk_descs[] = {
[TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_edp_clkref_en",
.offset = 0x60,
.regulator_names = glymur_tcsr_tx1_rpt0_rx0_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt0_rx0_regulators),
},
[TCSR_PCIE_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_1_clkref_en",
.offset = 0x48,
.regulator_names = glymur_tcsr_tx0_rx5_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators),
},
[TCSR_PCIE_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_2_clkref_en",
.offset = 0x4c,
.regulator_names = glymur_tcsr_tx1_rpt012_rx2_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators),
},
[TCSR_PCIE_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_3_clkref_en",
.offset = 0x54,
.regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators),
},
[TCSR_PCIE_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_4_clkref_en",
.offset = 0x58,
.regulator_names = glymur_tcsr_tx1_rpt012_rx2_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators),
},
[TCSR_USB2_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_1_clkref_en",
.offset = 0x6c,
.regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators),
},
[TCSR_USB2_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_2_clkref_en",
.offset = 0x70,
.regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators),
},
[TCSR_USB2_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_3_clkref_en",
.offset = 0x74,
.regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators),
},
[TCSR_USB2_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_4_clkref_en",
.offset = 0x88,
.regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators),
},
[TCSR_USB3_0_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb3_0_clkref_en",
.offset = 0x64,
.regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators),
},
[TCSR_USB3_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb3_1_clkref_en",
.offset = 0x68,
.regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators),
},
[TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb4_1_clkref_en",
.offset = 0x44,
.regulator_names = glymur_tcsr_tx0_rx5_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators),
},
[TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb4_2_clkref_en",
.offset = 0x5c,
.regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators),
},
};
static const struct of_device_id tcsr_cc_glymur_match_table[] = {
@ -285,7 +154,9 @@ MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table);
static int tcsr_cc_glymur_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &tcsr_cc_glymur_desc);
return qcom_clk_ref_probe(pdev, &tcsr_cc_glymur_regmap_config,
tcsr_cc_glymur_clk_descs,
ARRAY_SIZE(tcsr_cc_glymur_clk_descs));
}
static struct platform_driver tcsr_cc_glymur_driver = {