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drm/amd/display: Fix hard hang if DSC is disabled

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We want to calculate the DTB clock values when DSC is enabled; however,
this is not the current behavior implemented in DCN32. Right now, DML is
trying to calculate DSC values even if DSC is disabled; as a result, we
can have a hard hang due to wrong clock calculation. This commit fixes
this issue by moving the calculation after the DSC check.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira 2022-07-13 13:17:41 -04:00 committed by Alex Deucher
parent e6c64182ed
commit 074293dd9f
1 changed files with 12 additions and 7 deletions
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19
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
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@ -1686,17 +1686,22 @@ double dml32_RequiredDTBCLK(
unsigned int AudioRate,
unsigned int AudioLayout)
{
double PixelWordRate = PixelClock / (OutputFormat == dm_444 ? 1 : 2);
double HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp *
dml_ceil(HActive / DSCSlices, 1) / 8.0, 1) / 3.0, 1);
double HCBlank = 64 + 32 *
dml_ceil(AudioRate * (AudioLayout == 1 ? 1 : 0.25) * HTotal / (PixelClock * 1000), 1);
double AverageTribyteRate = PixelWordRate * (HCActive + HCBlank) / HTotal;
double HActiveTribyteRate = PixelWordRate * HCActive / HActive;
double PixelWordRate;
double HCActive;
double HCBlank;
double AverageTribyteRate;
double HActiveTribyteRate;
if (DSCEnable != true)
return dml_max(PixelClock / 4.0 * OutputBpp / 24.0, 25.0);
PixelWordRate = PixelClock / (OutputFormat == dm_444 ? 1 : 2);
HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp *
dml_ceil(HActive / DSCSlices, 1) / 8.0, 1) / 3.0, 1);
HCBlank = 64 + 32 *
dml_ceil(AudioRate * (AudioLayout == 1 ? 1 : 0.25) * HTotal / (PixelClock * 1000), 1);
AverageTribyteRate = PixelWordRate * (HCActive + HCBlank) / HTotal;
HActiveTribyteRate = PixelWordRate * HCActive / HActive;
return dml_max4(PixelWordRate / 4.0, AverageTribyteRate / 4.0, HActiveTribyteRate / 4.0, 25.0) * 1.002;
}