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staging: media: tegra-video: tegra20: increase maximum VI clock frequency

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Increase maximum VI clock frequency to 450MHz to allow correct work with
high resolution camera sensors.

Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Svyatoslav Ryhel 2026-03-03 10:42:35 +02:00 committed by Hans Verkuil
parent d8f8373f1a
commit 071fa83ded
1 changed files with 1 additions and 1 deletions
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2
drivers/staging/media/tegra-video/tegra20.c
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@ -598,7 +598,7 @@ const struct tegra_vi_soc tegra20_vi_soc = {
.ops = &tegra20_vi_ops,
.hw_revision = 1,
.vi_max_channels = 2, /* TEGRA_VI_OUT_1 and TEGRA_VI_OUT_2 */
.vi_max_clk_hz = 150000000,
.vi_max_clk_hz = 450000000,
.has_h_v_flip = true,
};