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drm/sun4i: Move blender config from layers to mixer
With upcoming DE33 support, layer management must be decoupled from other operations like blender configuration. There are two reasons: - DE33 will have separate driver for planes and thus it will be harder to manage different register spaces - Architecturaly it's better to split access by modules. Blender is now exclusively managed by mixer. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-8-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
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@ -284,8 +284,8 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
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drm_for_each_plane(plane, state->dev) {
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struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
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int w, h, x, y, zpos;
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bool enable;
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int zpos;
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if (!(plane->possible_crtcs & drm_crtc_mask(crtc)) || layer->mixer != mixer)
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continue;
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@ -296,10 +296,14 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
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enable = plane_state->crtc && plane_state->visible;
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zpos = plane_state->normalized_zpos;
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x = plane_state->dst.x1;
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y = plane_state->dst.y1;
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w = drm_rect_width(&plane_state->dst);
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h = drm_rect_height(&plane_state->dst);
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DRM_DEBUG_DRIVER(" plane %d: chan=%d ovl=%d en=%d zpos=%d\n",
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DRM_DEBUG_DRIVER(" plane %d: chan=%d ovl=%d en=%d zpos=%d x=%d y=%d w=%d h=%d\n",
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plane->base.id, layer->channel, layer->overlay,
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enable, zpos);
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enable, zpos, x, y, w, h);
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/*
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* We always update the layer enable bit, because it can clear
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@ -313,6 +317,13 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
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/* Route layer to pipe based on zpos */
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route |= layer->channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
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pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
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regmap_write(bld_regs,
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SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
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SUN8I_MIXER_COORD(x, y));
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regmap_write(bld_regs,
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SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
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SUN8I_MIXER_SIZE(w, h));
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}
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regmap_write(bld_regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route);
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@ -48,21 +48,17 @@ static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
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}
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static void sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane,
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unsigned int zpos)
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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u32 src_w, src_h, dst_w, dst_h;
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struct regmap *bld_regs;
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u32 bld_base, ch_base;
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u32 outsize, insize;
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u32 hphase, vphase;
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u32 ch_base;
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DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n",
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channel, overlay);
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bld_base = sun8i_blender_base(mixer);
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bld_regs = sun8i_blender_regmap(mixer);
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ch_base = sun8i_channel_base(mixer, channel);
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src_w = drm_rect_width(&state->src) >> 16;
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@ -114,17 +110,6 @@ static void sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
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else
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sun8i_ui_scaler_enable(mixer, channel, false);
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}
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/* Set base coordinates */
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DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
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state->dst.x1, state->dst.y1);
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DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
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regmap_write(bld_regs,
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SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
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SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
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regmap_write(bld_regs,
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SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
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outsize);
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}
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static void sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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@ -230,14 +215,13 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
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plane);
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struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
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unsigned int zpos = new_state->normalized_zpos;
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struct sun8i_mixer *mixer = layer->mixer;
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if (!new_state->crtc || !new_state->visible)
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return;
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sun8i_ui_layer_update_coord(mixer, layer->channel,
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layer->overlay, plane, zpos);
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layer->overlay, plane);
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sun8i_ui_layer_update_alpha(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_ui_layer_update_formats(mixer, layer->channel,
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@ -50,25 +50,21 @@ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
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}
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static void sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane,
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unsigned int zpos)
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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const struct drm_format_info *format = state->fb->format;
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u32 src_w, src_h, dst_w, dst_h;
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struct regmap *bld_regs;
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u32 bld_base, ch_base;
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u32 outsize, insize;
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u32 hphase, vphase;
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u32 hn = 0, hm = 0;
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u32 vn = 0, vm = 0;
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bool subsampled;
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u32 ch_base;
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DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n",
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channel, overlay);
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bld_base = sun8i_blender_base(mixer);
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bld_regs = sun8i_blender_regmap(mixer);
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ch_base = sun8i_channel_base(mixer, channel);
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src_w = drm_rect_width(&state->src) >> 16;
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@ -181,17 +177,6 @@ static void sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
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SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base),
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SUN8I_MIXER_CHAN_VI_DS_N(vn) |
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SUN8I_MIXER_CHAN_VI_DS_M(vm));
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/* Set base coordinates */
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DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
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state->dst.x1, state->dst.y1);
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DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
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regmap_write(bld_regs,
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SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
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SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
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regmap_write(bld_regs,
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SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
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outsize);
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}
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static u32 sun8i_vi_layer_get_csc_mode(const struct drm_format_info *format)
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@ -350,14 +335,13 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
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plane);
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struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
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unsigned int zpos = new_state->normalized_zpos;
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struct sun8i_mixer *mixer = layer->mixer;
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if (!new_state->crtc || !new_state->visible)
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return;
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sun8i_vi_layer_update_coord(mixer, layer->channel,
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layer->overlay, plane, zpos);
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layer->overlay, plane);
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sun8i_vi_layer_update_alpha(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_vi_layer_update_formats(mixer, layer->channel,
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