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drm/amd/display: Added multi instance support for panel control

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[Why]
Panel control always programs instance 0. With multi eDP we need to
support multiple instances.

[How]
Use link index to set different instances for panel control.
Refactored LVTMA control to support multiple instances.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jake Wang 2021-02-23 17:46:55 -05:00 committed by Alex Deucher
parent 1a595f28ea
commit 06ddcee49a
6 changed files with 33 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View File

@ -1180,14 +1180,15 @@ static enum bp_result bios_parser_enable_disp_power_gating(
static enum bp_result bios_parser_enable_lvtma_control(
struct dc_bios *dcb,
uint8_t uc_pwr_on)
uint8_t uc_pwr_on,
uint8_t panel_instance)
{
struct bios_parser *bp = BP_FROM_DCB(dcb);
if (!bp->cmd_tbl.enable_lvtma_control)
return BP_RESULT_FAILURE;
return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on);
return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance);
}
static bool bios_parser_is_accelerated_mode(

21
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
View File

@ -981,7 +981,8 @@ static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id)
static enum bp_result enable_lvtma_control(
struct bios_parser *bp,
uint8_t uc_pwr_on);
uint8_t uc_pwr_on,
uint8_t panel_instance);
static void init_enable_lvtma_control(struct bios_parser *bp)
{
@ -992,19 +993,21 @@ static void init_enable_lvtma_control(struct bios_parser *bp)
static void enable_lvtma_control_dmcub(
struct dc_dmub_srv *dmcub,
uint8_t uc_pwr_on)
uint8_t uc_pwr_on,
uint8_t panel_instance)
{
union dmub_rb_cmd cmd;
memset(&cmd, 0, sizeof(cmd));
cmd.cmd_common.header.type = DMUB_CMD__VBIOS;
cmd.cmd_common.header.sub_type =
cmd.lvtma_control.header.type = DMUB_CMD__VBIOS;
cmd.lvtma_control.header.sub_type =
DMUB_CMD__VBIOS_LVTMA_CONTROL;
cmd.cmd_common.cmd_buffer[0] =
cmd.lvtma_control.data.uc_pwr_action =
uc_pwr_on;
cmd.lvtma_control.data.panel_inst =
panel_instance;
dc_dmub_srv_cmd_queue(dmcub, &cmd);
dc_dmub_srv_cmd_execute(dmcub);
dc_dmub_srv_wait_idle(dmcub);
@ -1013,14 +1016,16 @@ static void enable_lvtma_control_dmcub(
static enum bp_result enable_lvtma_control(
struct bios_parser *bp,
uint8_t uc_pwr_on)
uint8_t uc_pwr_on,
uint8_t panel_instance)
{
enum bp_result result = BP_RESULT_FAILURE;
if (bp->base.ctx->dc->ctx->dmub_srv &&
bp->base.ctx->dc->debug.dmub_command_table) {
enable_lvtma_control_dmcub(bp->base.ctx->dmub_srv,
uc_pwr_on);
uc_pwr_on,
panel_instance);
return BP_RESULT_OK;
}
return result;

3
drivers/gpu/drm/amd/display/dc/bios/command_table2.h
View File

@ -95,7 +95,8 @@ struct cmd_tbl {
unsigned int (*get_smu_clock_info)(
struct bios_parser *bp, uint8_t id);
enum bp_result (*enable_lvtma_control)(struct bios_parser *bp,
uint8_t uc_pwr_on);
uint8_t uc_pwr_on,
uint8_t panel_instance);
};
void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp);

2
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -1506,7 +1506,7 @@ static bool dc_link_construct(struct dc_link *link,
(link->link_id.id == CONNECTOR_ID_EDP ||
link->link_id.id == CONNECTOR_ID_LVDS)) {
panel_cntl_init_data.ctx = dc_ctx;
panel_cntl_init_data.inst = 0;
panel_cntl_init_data.inst = link->link_index;
link->panel_cntl =
link->dc->res_pool->funcs->panel_cntl_create(
&panel_cntl_init_data);

3
drivers/gpu/drm/amd/display/dc/dc_bios_types.h
View File

@ -139,7 +139,8 @@ struct dc_vbios_funcs {
enum bp_result (*enable_lvtma_control)(
struct dc_bios *bios,
uint8_t uc_pwr_on);
uint8_t uc_pwr_on,
uint8_t panel_instance);
enum bp_result (*get_soc_bb_info)(
struct dc_bios *dcb,

17
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -797,6 +797,7 @@ void dce110_edp_power_control(
struct dc_context *ctx = link->ctx;
struct bp_transmitter_control cntl = { 0 };
enum bp_result bp_result;
uint8_t panel_instance;
if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
@ -807,7 +808,6 @@ void dce110_edp_power_control(
if (!link->panel_cntl)
return;
if (power_up !=
link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
@ -880,15 +880,18 @@ void dce110_edp_power_control(
cntl.coherent = false;
cntl.lanes_number = LANE_COUNT_FOUR;
cntl.hpd_sel = link->link_enc->hpd_source;
panel_instance = link->panel_cntl->inst;
if (ctx->dc->ctx->dmub_srv &&
ctx->dc->debug.dmub_command_table) {
if (cntl.action == TRANSMITTER_CONTROL_POWER_ON)
bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
LVTMA_CONTROL_POWER_ON);
LVTMA_CONTROL_POWER_ON,
panel_instance);
else
bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
LVTMA_CONTROL_POWER_OFF);
LVTMA_CONTROL_POWER_OFF,
panel_instance);
}
bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
@ -963,6 +966,7 @@ void dce110_edp_backlight_control(
{
struct dc_context *ctx = link->ctx;
struct bp_transmitter_control cntl = { 0 };
uint8_t panel_instance;
if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
!= CONNECTOR_ID_EDP) {
@ -1011,6 +1015,7 @@ void dce110_edp_backlight_control(
*/
/* dc_service_sleep_in_milliseconds(50); */
/*edp 1.2*/
panel_instance = link->panel_cntl->inst;
if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
edp_receiver_ready_T7(link);
@ -1018,10 +1023,12 @@ void dce110_edp_backlight_control(
ctx->dc->debug.dmub_command_table) {
if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
LVTMA_CONTROL_LCD_BLON);
LVTMA_CONTROL_LCD_BLON,
panel_instance);
else
ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
LVTMA_CONTROL_LCD_BLOFF);
LVTMA_CONTROL_LCD_BLOFF,
panel_instance);
}
link_transmitter_control(ctx->dc_bios, &cntl);