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arm64: dts: imx8: create unified pcie0 and pcie0_ep label for all chips
Add unified pcie<n> and pcie<n>_ep label for existed chipes to prepare applied one overay file to enable EP function. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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06d9879c10
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@ -37,15 +37,18 @@ hsio_phy: phy@5f1a0000 {
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power-domains = <&pd IMX_SC_R_SERDES_1>;
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status = "disabled";
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};
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};
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&pcieb {
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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interrupt-map = <0 0 0 1 &gic 0 47 4>,
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<0 0 0 2 &gic 0 48 4>,
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<0 0 0 3 &gic 0 49 4>,
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<0 0 0 4 &gic 0 50 4>;
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interrupt-map-mask = <0 0 0 0x7>;
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pcie0: pcie@5f010000 {
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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interrupt-map = <0 0 0 1 &gic 0 47 4>,
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<0 0 0 2 &gic 0 48 4>,
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<0 0 0 3 &gic 0 49 4>,
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<0 0 0 4 &gic 0 50 4>;
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interrupt-map-mask = <0 0 0 0x7>;
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};
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pcie0_ep: pcie-ep@5f010000 {
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};
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};
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@ -2153,7 +2153,7 @@ hdmi_tx_phy: phy@32fdff00 {
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};
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};
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pcie: pcie@33800000 {
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pcie0: pcie: pcie@33800000 {
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compatible = "fsl,imx8mp-pcie";
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reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
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reg-names = "dbi", "config";
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@ -2191,7 +2191,7 @@ pcie: pcie@33800000 {
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status = "disabled";
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};
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pcie_ep: pcie-ep@33800000 {
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pcie0_ep: pcie_ep: pcie-ep@33800000 {
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compatible = "fsl,imx8mp-pcie-ep";
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reg = <0x33800000 0x100000>,
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<0x18000000 0x8000000>,
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@ -12,7 +12,7 @@ &hsio_subsys {
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#address-cells = <1>;
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#size-cells = <1>;
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pciea: pcie@5f000000 {
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pcie0: pciea: pcie@5f000000 {
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compatible = "fsl,imx8q-pcie";
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reg = <0x5f000000 0x10000>,
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<0x4ff00000 0x80000>;
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@ -42,7 +42,7 @@ pciea: pcie@5f000000 {
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status = "disabled";
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};
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pciea_ep: pcie-ep@5f000000 {
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pcie0_ep: pciea_ep: pcie-ep@5f000000 {
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compatible = "fsl,imx8q-pcie-ep";
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reg = <0x5f000000 0x00010000>,
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<0x40000000 0x10000000>;
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@ -61,7 +61,7 @@ pciea_ep: pcie-ep@5f000000 {
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status = "disabled";
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};
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pcieb: pcie@5f010000 {
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pcie1: pcieb: pcie@5f010000 {
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compatible = "fsl,imx8q-pcie";
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reg = <0x5f010000 0x10000>,
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<0x8ff00000 0x80000>;
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@ -38,4 +38,10 @@ hsio_phy: phy@5f1a0000 {
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power-domains = <&pd IMX_SC_R_SERDES_1>;
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status = "disabled";
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};
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pcie0: pcie@5f010000 {
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};
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pcie0_ep: pcie-ep@5f010000 {
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};
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};
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