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RISC-V: validate riscv,isa at boot, not during ISA string parsing

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Since riscv_fill_hwcap() now only iterates over possible cpus, the
basic validation of whether riscv,isa contains "rv<width>" can be moved
to riscv_early_of_processor_hartid().

Further, "ima" support is required by the kernel, so reject any CPU not
fitting the bill.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Link: https://lore.kernel.org/r/20230607-guts-blurry-67e711acf328@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Conor Dooley 2023-06-07 21:28:27 +01:00 committed by Palmer Dabbelt
parent 2ac8743437
commit 069b0d5170
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
2 changed files with 11 additions and 9 deletions
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8
arch/riscv/kernel/cpu.c
View File

@ -65,10 +65,12 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
return -ENODEV;
}
if (tolower(isa[0]) != 'r' || tolower(isa[1]) != 'v') {
pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7))
return -ENODEV;
if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7))
return -ENODEV;
}
return 0;
}

12
arch/riscv/kernel/cpufeature.c
View File

@ -148,12 +148,12 @@ void __init riscv_fill_hwcap(void)
}
}
if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32", 4))
continue;
if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64", 4))
continue;
/*
* For all possible cpus, we have already validated in
* the boot process that they at least contain "rv" and
* whichever of "32"/"64" this kernel supports, and so this
* section can be skipped.
*/
isa += 4;
bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);