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arm64: dts: qcom: sm8150: Define CPU topology

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sm8150 has a big.LITTLE CPU setup with DynamIQ, so all cores are within
the same CPU cluster and LLC (Last-Level Cache) domain. Define this
topology to help the scheduler make decisions.

Signed-off-by: Danny Lin <danny@kdrag0n.dev>
Link: https://lore.kernel.org/r/20201221002907.2870059-2-danny@kdrag0n.dev
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Danny Lin 2020-12-20 16:29:05 -08:00 committed by Bjorn Andersson
parent 8d079bf204
commit 066d21bcf6
1 changed files with 36 additions and 0 deletions
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36
arch/arm64/boot/dts/qcom/sm8150.dtsi
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@ -157,6 +157,42 @@ L2_700: l2-cache {
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
};
firmware {