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Merge branches '20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com' and '20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org' into arm64-for-6.14

Browse Source 
Merge SM8750 gcc, tcsr and display clock bindings from topic branches,
to gain access to clock constants.
This commit is contained in:
Bjorn Andersson 2025-01-06 10:36:43 -06:00
commit 05d5d3840b
6 changed files with 420 additions and 1 deletions
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4
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
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@ -12,11 +12,12 @@ maintainers:
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8550.
domains on SM8550, SM8650, SM8750 and few other platforms.
See also:
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
properties:
@ -25,6 +26,7 @@ properties:
- qcom,sar2130p-dispcc
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc
- qcom,sm8750-dispcc
- qcom,x1e80100-dispcc
clocks:

2
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
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@ -16,6 +16,7 @@ description: |
See also:
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
properties:
compatible:
@ -24,6 +25,7 @@ properties:
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,sm8750-tcsr
- qcom,x1e80100-tcsr
- const: syscon

62
Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml Normal file
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@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8750-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM8750
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8750
See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
properties:
compatible:
const: qcom,sm8750-gcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm8750-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&pcie0_phy>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

112
include/dt-bindings/clock/qcom,sm8750-dispcc.h Normal file
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@ -0,0 +1,112 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024, Linaro Ltd.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H
#define _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H
/* DISP_CC clocks */
#define DISP_CC_ESYNC0_CLK 0
#define DISP_CC_ESYNC0_CLK_SRC 1
#define DISP_CC_ESYNC1_CLK 2
#define DISP_CC_ESYNC1_CLK_SRC 3
#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4
#define DISP_CC_MDSS_AHB1_CLK 5
#define DISP_CC_MDSS_AHB_CLK 6
#define DISP_CC_MDSS_AHB_CLK_SRC 7
#define DISP_CC_MDSS_BYTE0_CLK 8
#define DISP_CC_MDSS_BYTE0_CLK_SRC 9
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 10
#define DISP_CC_MDSS_BYTE0_INTF_CLK 11
#define DISP_CC_MDSS_BYTE1_CLK 12
#define DISP_CC_MDSS_BYTE1_CLK_SRC 13
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 14
#define DISP_CC_MDSS_BYTE1_INTF_CLK 15
#define DISP_CC_MDSS_DPTX0_AUX_CLK 16
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 17
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 18
#define DISP_CC_MDSS_DPTX0_LINK_CLK 19
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 20
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 21
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 22
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 23
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 24
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 25
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 26
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27
#define DISP_CC_MDSS_DPTX1_AUX_CLK 28
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30
#define DISP_CC_MDSS_DPTX1_LINK_CLK 31
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 32
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 33
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 34
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 35
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 36
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 37
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 38
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 39
#define DISP_CC_MDSS_DPTX2_AUX_CLK 40
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 41
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 42
#define DISP_CC_MDSS_DPTX2_LINK_CLK 43
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 44
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 45
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 46
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 47
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 48
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 49
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 50
#define DISP_CC_MDSS_DPTX3_AUX_CLK 51
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 52
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 53
#define DISP_CC_MDSS_DPTX3_LINK_CLK 54
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 55
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 56
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 57
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 58
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 59
#define DISP_CC_MDSS_ESC0_CLK 60
#define DISP_CC_MDSS_ESC0_CLK_SRC 61
#define DISP_CC_MDSS_ESC1_CLK 62
#define DISP_CC_MDSS_ESC1_CLK_SRC 63
#define DISP_CC_MDSS_MDP1_CLK 64
#define DISP_CC_MDSS_MDP_CLK 65
#define DISP_CC_MDSS_MDP_CLK_SRC 66
#define DISP_CC_MDSS_MDP_LUT1_CLK 67
#define DISP_CC_MDSS_MDP_LUT_CLK 68
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 69
#define DISP_CC_MDSS_PCLK0_CLK 70
#define DISP_CC_MDSS_PCLK0_CLK_SRC 71
#define DISP_CC_MDSS_PCLK1_CLK 72
#define DISP_CC_MDSS_PCLK1_CLK_SRC 73
#define DISP_CC_MDSS_PCLK2_CLK 74
#define DISP_CC_MDSS_PCLK2_CLK_SRC 75
#define DISP_CC_MDSS_RSCC_AHB_CLK 76
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 77
#define DISP_CC_MDSS_VSYNC1_CLK 78
#define DISP_CC_MDSS_VSYNC_CLK 79
#define DISP_CC_MDSS_VSYNC_CLK_SRC 80
#define DISP_CC_OSC_CLK 81
#define DISP_CC_OSC_CLK_SRC 82
#define DISP_CC_PLL0 83
#define DISP_CC_PLL1 84
#define DISP_CC_PLL2 85
#define DISP_CC_SLEEP_CLK 86
#define DISP_CC_SLEEP_CLK_SRC 87
#define DISP_CC_XO_CLK 88
#define DISP_CC_XO_CLK_SRC 89
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#define MDSS_INT2_GDSC 1
#endif

226
include/dt-bindings/clock/qcom,sm8750-gcc.h Normal file
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@ -0,0 +1,226 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
#define GCC_BOOT_ROM_AHB_CLK 4
#define GCC_CAM_BIST_MCLK_AHB_CLK 5
#define GCC_CAMERA_AHB_CLK 6
#define GCC_CAMERA_HF_AXI_CLK 7
#define GCC_CAMERA_SF_AXI_CLK 8
#define GCC_CAMERA_XO_CLK 9
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11
#define GCC_CNOC_PCIE_SF_AXI_CLK 12
#define GCC_DDRSS_GPU_AXI_CLK 13
#define GCC_DDRSS_PCIE_SF_QTB_CLK 14
#define GCC_DISP_AHB_CLK 15
#define GCC_DISP_HF_AXI_CLK 16
#define GCC_EVA_AHB_CLK 17
#define GCC_EVA_AXI0_CLK 18
#define GCC_EVA_AXI0C_CLK 19
#define GCC_EVA_XO_CLK 20
#define GCC_GP1_CLK 21
#define GCC_GP1_CLK_SRC 22
#define GCC_GP2_CLK 23
#define GCC_GP2_CLK_SRC 24
#define GCC_GP3_CLK 25
#define GCC_GP3_CLK_SRC 26
#define GCC_GPLL0 27
#define GCC_GPLL0_OUT_EVEN 28
#define GCC_GPLL1 29
#define GCC_GPLL4 30
#define GCC_GPLL7 31
#define GCC_GPLL9 32
#define GCC_GPU_CFG_AHB_CLK 33
#define GCC_GPU_GEMNOC_GFX_CLK 34
#define GCC_GPU_GPLL0_CLK_SRC 35
#define GCC_GPU_GPLL0_DIV_CLK_SRC 36
#define GCC_PCIE_0_AUX_CLK 37
#define GCC_PCIE_0_AUX_CLK_SRC 38
#define GCC_PCIE_0_CFG_AHB_CLK 39
#define GCC_PCIE_0_MSTR_AXI_CLK 40
#define GCC_PCIE_0_PHY_RCHNG_CLK 41
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
#define GCC_PCIE_0_PIPE_CLK 43
#define GCC_PCIE_0_PIPE_CLK_SRC 44
#define GCC_PCIE_0_SLV_AXI_CLK 45
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 46
#define GCC_PCIE_RSCC_CFG_AHB_CLK 47
#define GCC_PCIE_RSCC_XO_CLK 48
#define GCC_PDM2_CLK 49
#define GCC_PDM2_CLK_SRC 50
#define GCC_PDM_AHB_CLK 51
#define GCC_PDM_XO4_CLK 52
#define GCC_QMIP_CAMERA_CMD_AHB_CLK 53
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 54
#define GCC_QMIP_CAMERA_RT_AHB_CLK 55
#define GCC_QMIP_GPU_AHB_CLK 56
#define GCC_QMIP_PCIE_AHB_CLK 57
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 58
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 59
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 60
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 61
#define GCC_QUPV3_I2C_CORE_CLK 62
#define GCC_QUPV3_I2C_S0_CLK 63
#define GCC_QUPV3_I2C_S0_CLK_SRC 64
#define GCC_QUPV3_I2C_S1_CLK 65
#define GCC_QUPV3_I2C_S1_CLK_SRC 66
#define GCC_QUPV3_I2C_S2_CLK 67
#define GCC_QUPV3_I2C_S2_CLK_SRC 68
#define GCC_QUPV3_I2C_S3_CLK 69
#define GCC_QUPV3_I2C_S3_CLK_SRC 70
#define GCC_QUPV3_I2C_S4_CLK 71
#define GCC_QUPV3_I2C_S4_CLK_SRC 72
#define GCC_QUPV3_I2C_S5_CLK 73
#define GCC_QUPV3_I2C_S5_CLK_SRC 74
#define GCC_QUPV3_I2C_S6_CLK 75
#define GCC_QUPV3_I2C_S6_CLK_SRC 76
#define GCC_QUPV3_I2C_S7_CLK 77
#define GCC_QUPV3_I2C_S7_CLK_SRC 78
#define GCC_QUPV3_I2C_S8_CLK 79
#define GCC_QUPV3_I2C_S8_CLK_SRC 80
#define GCC_QUPV3_I2C_S9_CLK 81
#define GCC_QUPV3_I2C_S9_CLK_SRC 82
#define GCC_QUPV3_I2C_S_AHB_CLK 83
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 84
#define GCC_QUPV3_WRAP1_CORE_CLK 85
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 86
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 87
#define GCC_QUPV3_WRAP1_S0_CLK 88
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89
#define GCC_QUPV3_WRAP1_S1_CLK 90
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91
#define GCC_QUPV3_WRAP1_S2_CLK 92
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93
#define GCC_QUPV3_WRAP1_S3_CLK 94
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95
#define GCC_QUPV3_WRAP1_S4_CLK 96
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97
#define GCC_QUPV3_WRAP1_S5_CLK 98
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99
#define GCC_QUPV3_WRAP1_S6_CLK 100
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101
#define GCC_QUPV3_WRAP1_S7_CLK 102
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 104
#define GCC_QUPV3_WRAP2_CORE_CLK 105
#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 106
#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 107
#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 108
#define GCC_QUPV3_WRAP2_S0_CLK 109
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110
#define GCC_QUPV3_WRAP2_S1_CLK 111
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112
#define GCC_QUPV3_WRAP2_S2_CLK 113
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114
#define GCC_QUPV3_WRAP2_S3_CLK 115
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116
#define GCC_QUPV3_WRAP2_S4_CLK 117
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118
#define GCC_QUPV3_WRAP2_S5_CLK 119
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120
#define GCC_QUPV3_WRAP2_S6_CLK 121
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 122
#define GCC_QUPV3_WRAP2_S7_CLK 123
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 124
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 125
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 126
#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 127
#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 128
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 129
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 130
#define GCC_SDCC2_AHB_CLK 131
#define GCC_SDCC2_APPS_CLK 132
#define GCC_SDCC2_APPS_CLK_SRC 133
#define GCC_SDCC4_AHB_CLK 134
#define GCC_SDCC4_APPS_CLK 135
#define GCC_SDCC4_APPS_CLK_SRC 136
#define GCC_UFS_PHY_AHB_CLK 137
#define GCC_UFS_PHY_AXI_CLK 138
#define GCC_UFS_PHY_AXI_CLK_SRC 139
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 140
#define GCC_UFS_PHY_ICE_CORE_CLK 141
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 142
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 143
#define GCC_UFS_PHY_PHY_AUX_CLK 144
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 145
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 146
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 147
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 148
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 149
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 150
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 151
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 152
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 153
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 154
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 155
#define GCC_USB30_PRIM_MASTER_CLK 156
#define GCC_USB30_PRIM_MASTER_CLK_SRC 157
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 158
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 159
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 160
#define GCC_USB30_PRIM_SLEEP_CLK 161
#define GCC_USB3_PRIM_PHY_AUX_CLK 162
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 163
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 164
#define GCC_USB3_PRIM_PHY_PIPE_CLK 165
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 166
#define GCC_VIDEO_AHB_CLK 167
#define GCC_VIDEO_AXI0_CLK 168
#define GCC_VIDEO_AXI1_CLK 169
#define GCC_VIDEO_XO_CLK 170
/* GCC power domains */
#define GCC_PCIE_0_GDSC 0
#define GCC_PCIE_0_PHY_GDSC 1
#define GCC_UFS_MEM_PHY_GDSC 2
#define GCC_UFS_PHY_GDSC 3
#define GCC_USB30_PRIM_GDSC 4
#define GCC_USB3_PHY_GDSC 5
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_EVA_BCR 2
#define GCC_GPU_BCR 3
#define GCC_PCIE_0_BCR 4
#define GCC_PCIE_0_LINK_DOWN_BCR 5
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
#define GCC_PCIE_0_PHY_BCR 7
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
#define GCC_PCIE_PHY_BCR 9
#define GCC_PCIE_PHY_CFG_AHB_BCR 10
#define GCC_PCIE_PHY_COM_BCR 11
#define GCC_PCIE_RSCC_BCR 12
#define GCC_PDM_BCR 13
#define GCC_QUPV3_WRAPPER_1_BCR 14
#define GCC_QUPV3_WRAPPER_2_BCR 15
#define GCC_QUPV3_WRAPPER_I2C_BCR 16
#define GCC_QUSB2PHY_PRIM_BCR 17
#define GCC_QUSB2PHY_SEC_BCR 18
#define GCC_SDCC2_BCR 19
#define GCC_SDCC4_BCR 20
#define GCC_UFS_PHY_BCR 21
#define GCC_USB30_PRIM_BCR 22
#define GCC_USB3_DP_PHY_PRIM_BCR 23
#define GCC_USB3_DP_PHY_SEC_BCR 24
#define GCC_USB3_PHY_PRIM_BCR 25
#define GCC_USB3_PHY_SEC_BCR 26
#define GCC_USB3PHY_PHY_PRIM_BCR 27
#define GCC_USB3PHY_PHY_SEC_BCR 28
#define GCC_VIDEO_AXI0_CLK_ARES 29
#define GCC_VIDEO_AXI1_CLK_ARES 30
#define GCC_VIDEO_BCR 31
#define GCC_EVA_AXI0_CLK_ARES 32
#define GCC_EVA_AXI0C_CLK_ARES 33
#endif

15
include/dt-bindings/clock/qcom,sm8750-tcsr.h Normal file
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@ -0,0 +1,15 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H
#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H
/* TCSR_CC clocks */
#define TCSR_PCIE_0_CLKREF_EN 0
#define TCSR_UFS_CLKREF_EN 1
#define TCSR_USB2_CLKREF_EN 2
#define TCSR_USB3_CLKREF_EN 3
#endif