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x86/cacheinfo: Extract out cache self-snoop checks

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The logic of not doing a cache flush if the CPU declares cache self
snooping support is repeated across the x86/cacheinfo code.  Extract it
into its own function.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20250324133324.23458-27-darwi@linutronix.de
This commit is contained in:
Ahmed S. Darwish 2025-03-24 14:33:21 +01:00 committed by Ingo Molnar
parent fda5f817ae
commit 05d48035e5
1 changed files with 13 additions and 11 deletions
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24
arch/x86/kernel/cpu/cacheinfo.c
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@ -646,6 +646,17 @@ int populate_cache_leaves(unsigned int cpu)
static unsigned long saved_cr4;
static DEFINE_RAW_SPINLOCK(cache_disable_lock);
/*
* Cache flushing is the most time-consuming step when programming the
* MTRRs. On many Intel CPUs without known erratas, it can be skipped
* if the CPU declares cache self-snooping support.
*/
static void maybe_flush_caches(void)
{
if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
wbinvd();
}
void cache_disable(void) __acquires(cache_disable_lock)
{
unsigned long cr0;
@ -663,14 +674,7 @@ void cache_disable(void) __acquires(cache_disable_lock)
cr0 = read_cr0() | X86_CR0_CD;
write_cr0(cr0);
/*
* Cache flushing is the most time-consuming step when programming
* the MTRRs. Fortunately, as per the Intel Software Development
* Manual, we can skip it if the processor supports cache self-
* snooping.
*/
if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
wbinvd();
maybe_flush_caches();
/* Save value of CR4 and clear Page Global Enable (bit 7) */
if (cpu_feature_enabled(X86_FEATURE_PGE)) {
@ -685,9 +689,7 @@ void cache_disable(void) __acquires(cache_disable_lock)
if (cpu_feature_enabled(X86_FEATURE_MTRR))
mtrr_disable();
/* Again, only flush caches if we have to. */
if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
wbinvd();
maybe_flush_caches();
}
void cache_enable(void) __releases(cache_disable_lock)