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KVM: SVM: Track per-vCPU IRTEs using kvm_kernel_irqfd structure
Track the IRTEs that are posting to an SVM vCPU via the associated irqfd structure and GSI routing instead of dynamically allocating a separate data structure. In addition to eliminating an atomic allocation, this will allow hoisting much of the IRTE update logic to common x86. Cc: Sairaj Kodilkar <sarunkod@amd.com> Link: https://lore.kernel.org/r/20250611224604.313496-6-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
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cb21073767
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@ -76,14 +76,6 @@ static bool next_vm_id_wrapped = 0;
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static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
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bool x2avic_enabled;
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/*
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* This is a wrapper of struct amd_iommu_ir_data.
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*/
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struct amd_svm_iommu_ir {
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struct list_head node; /* Used by SVM for per-vcpu ir_list */
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void *data; /* Storing pointer to struct amd_ir_data */
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};
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static void avic_activate_vmcb(struct vcpu_svm *svm)
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{
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struct vmcb *vmcb = svm->vmcb01.ptr;
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@ -747,8 +739,8 @@ static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate)
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{
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int ret = 0;
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unsigned long flags;
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struct amd_svm_iommu_ir *ir;
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struct vcpu_svm *svm = to_svm(vcpu);
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struct kvm_kernel_irqfd *irqfd;
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if (!kvm_arch_has_assigned_device(vcpu->kvm))
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return 0;
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@ -762,11 +754,11 @@ static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate)
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if (list_empty(&svm->ir_list))
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goto out;
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list_for_each_entry(ir, &svm->ir_list, node) {
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list_for_each_entry(irqfd, &svm->ir_list, vcpu_list) {
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if (activate)
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ret = amd_iommu_activate_guest_mode(ir->data);
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ret = amd_iommu_activate_guest_mode(irqfd->irq_bypass_data);
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else
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ret = amd_iommu_deactivate_guest_mode(ir->data);
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ret = amd_iommu_deactivate_guest_mode(irqfd->irq_bypass_data);
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if (ret)
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break;
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}
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@ -775,27 +767,30 @@ static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate)
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return ret;
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}
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static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
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static void svm_ir_list_del(struct vcpu_svm *svm,
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struct kvm_kernel_irqfd *irqfd,
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struct amd_iommu_pi_data *pi)
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{
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unsigned long flags;
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struct amd_svm_iommu_ir *cur;
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struct kvm_kernel_irqfd *cur;
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spin_lock_irqsave(&svm->ir_list_lock, flags);
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list_for_each_entry(cur, &svm->ir_list, node) {
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if (cur->data != pi->ir_data)
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list_for_each_entry(cur, &svm->ir_list, vcpu_list) {
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if (cur->irq_bypass_data != pi->ir_data)
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continue;
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list_del(&cur->node);
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kfree(cur);
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if (WARN_ON_ONCE(cur != irqfd))
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continue;
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list_del(&irqfd->vcpu_list);
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break;
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}
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spin_unlock_irqrestore(&svm->ir_list_lock, flags);
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}
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static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
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static int svm_ir_list_add(struct vcpu_svm *svm,
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struct kvm_kernel_irqfd *irqfd,
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struct amd_iommu_pi_data *pi)
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{
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int ret = 0;
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unsigned long flags;
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struct amd_svm_iommu_ir *ir;
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u64 entry;
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if (WARN_ON_ONCE(!pi->ir_data))
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@ -812,25 +807,14 @@ static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
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struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
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struct vcpu_svm *prev_svm;
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if (!prev_vcpu) {
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ret = -EINVAL;
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goto out;
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}
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if (!prev_vcpu)
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return -EINVAL;
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prev_svm = to_svm(prev_vcpu);
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svm_ir_list_del(prev_svm, pi);
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svm_ir_list_del(prev_svm, irqfd, pi);
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}
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/**
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* Allocating new amd_iommu_pi_data, which will get
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* add to the per-vcpu ir_list.
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*/
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ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_ATOMIC | __GFP_ACCOUNT);
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if (!ir) {
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ret = -ENOMEM;
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goto out;
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}
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ir->data = pi->ir_data;
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irqfd->irq_bypass_data = pi->ir_data;
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spin_lock_irqsave(&svm->ir_list_lock, flags);
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@ -845,10 +829,9 @@ static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
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amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK,
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true, pi->ir_data);
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list_add(&ir->node, &svm->ir_list);
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list_add(&irqfd->vcpu_list, &svm->ir_list);
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spin_unlock_irqrestore(&svm->ir_list_lock, flags);
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out:
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return ret;
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return 0;
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}
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/*
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@ -952,7 +935,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm,
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* scheduling information in IOMMU irte.
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*/
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if (!ret && pi.is_guest_mode)
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svm_ir_list_add(svm, &pi);
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svm_ir_list_add(svm, irqfd, &pi);
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}
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if (!ret && svm) {
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@ -993,7 +976,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm,
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vcpu = kvm_get_vcpu_by_id(kvm, id);
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if (vcpu)
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svm_ir_list_del(to_svm(vcpu), &pi);
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svm_ir_list_del(to_svm(vcpu), irqfd, &pi);
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}
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}
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out:
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@ -1005,8 +988,8 @@ static inline int
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avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
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{
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int ret = 0;
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struct amd_svm_iommu_ir *ir;
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struct vcpu_svm *svm = to_svm(vcpu);
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struct kvm_kernel_irqfd *irqfd;
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lockdep_assert_held(&svm->ir_list_lock);
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@ -1020,8 +1003,8 @@ avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
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if (list_empty(&svm->ir_list))
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return 0;
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list_for_each_entry(ir, &svm->ir_list, node) {
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ret = amd_iommu_update_ga(cpu, r, ir->data);
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list_for_each_entry(irqfd, &svm->ir_list, vcpu_list) {
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ret = amd_iommu_update_ga(cpu, r, irqfd->irq_bypass_data);
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if (ret)
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return ret;
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}
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@ -310,10 +310,12 @@ struct vcpu_svm {
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u64 *avic_physical_id_cache;
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/*
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* Per-vcpu list of struct amd_svm_iommu_ir:
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* This is used mainly to store interrupt remapping information used
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* when update the vcpu affinity. This avoids the need to scan for
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* IRTE and try to match ga_tag in the IOMMU driver.
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* Per-vCPU list of irqfds that are eligible to post IRQs directly to
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* the vCPU (a.k.a. device posted IRQs, a.k.a. IRQ bypass). The list
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* is used to reconfigure IRTEs when the vCPU is loaded/put (to set the
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* target pCPU), when AVIC is toggled on/off (to (de)activate bypass),
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* and if the irqfd becomes ineligible for posting (to put the IRTE
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* back into remapped mode).
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*/
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struct list_head ir_list;
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spinlock_t ir_list_lock;
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@ -59,6 +59,9 @@ struct kvm_kernel_irqfd {
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struct work_struct shutdown;
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struct irq_bypass_consumer consumer;
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struct irq_bypass_producer *producer;
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struct list_head vcpu_list;
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void *irq_bypass_data;
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};
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#endif /* __LINUX_KVM_IRQFD_H */
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