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Added H6 RTC clock and H616 32 kHz clock

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Merge tag 'sunxi-clk-for-5.19-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Jernej Skrabec:

 - Allwinner H6 RTC clock
 - Allwinner H616 32 kHz clock

* tag 'sunxi-clk-for-5.19-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: h616: Add PLL derived 32KHz clock
  clk: sunxi-ng: h6-r: Add RTC gate clock
This commit is contained in:
Stephen Boyd 2022-05-16 23:56:23 -07:00
commit 0594058b72
6 changed files with 17 additions and 2 deletions
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5
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
View File

@ -98,6 +98,8 @@ static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
0x1ec, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_rtc_clk, "r-apb1-rtc", "r-apb1",
0x20c, BIT(0), CLK_IGNORE_UNUSED);
/* Information of IR(RX) mod clock is gathered from BSP source code */
static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
@ -147,6 +149,7 @@ static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
&r_apb2_i2c_clk.common,
&r_apb2_rsb_clk.common,
&r_apb1_ir_clk.common,
&r_apb1_rtc_clk.common,
&ir_clk.common,
};
@ -164,6 +167,7 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
[CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
[CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
[CLK_R_APB1_W1] = &r_apb1_w1_clk.common.hw,
[CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
[CLK_W1] = &w1_clk.common.hw,
},
@ -179,6 +183,7 @@ static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
[CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
[CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
[CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
[CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
},
.num = CLK_NUMBER,

2
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
View File

@ -14,6 +14,6 @@
#define CLK_R_APB2 3
#define CLK_NUMBER (CLK_R_APB2_RSB + 1)
#define CLK_NUMBER (CLK_R_APB1_RTC + 1)
#endif /* _CCU_SUN50I_H6_R_H */

8
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
View File

@ -704,6 +704,13 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
pll_periph0_parents,
1, 2, 0);
static const struct clk_hw *pll_periph0_2x_hws[] = {
&pll_periph0_2x_clk.hw
};
static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k",
pll_periph0_2x_hws, 36621, 1, 0);
static const struct clk_hw *pll_periph1_parents[] = {
&pll_periph1_clk.common.hw
};
@ -852,6 +859,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
[CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
[CLK_PLL_SYSTEM_32K] = &pll_system_32k_clk.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,

2
drivers/clk/sunxi-ng/ccu-sun50i-h616.h
View File

@ -51,6 +51,6 @@
#define CLK_BUS_DRAM 56
#define CLK_NUMBER (CLK_BUS_HDCP + 1)
#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1)
#endif /* _CCU_SUN50I_H616_H_ */

1
include/dt-bindings/clock/sun50i-h6-r-ccu.h
View File

@ -22,5 +22,6 @@
#define CLK_W1 12
#define CLK_R_APB2_RSB 13
#define CLK_R_APB1_RTC 14
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */

1
include/dt-bindings/clock/sun50i-h616-ccu.h
View File

@ -111,5 +111,6 @@
#define CLK_BUS_TVE0 125
#define CLK_HDCP 126
#define CLK_BUS_HDCP 127
#define CLK_PLL_SYSTEM_32K 128
#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */